EMC discussion

As I think, many FPGA-designers have also to deal with EMC, I hope
someone can help me here. We have currently some discussions (and
doubts) regarding EMC-topics. As many people have different opinions
on this subject, and it is quite hard to objectively verify, I would
like to ask for some comments about following:

1. Filtering of IC-supply-voltage
While it is quite standard to filter e.g. the PLL-supply voltages of a
FPGA, there are some suggestions to filter the supply-voltage of every
IC (CPU, FPGA, memory, ...) on the PCB with a ferrite-bead + C.
(Consequently, this also means that every IC has it's own Vdd-island
in the power-plane.) Does this work?

2. Return-path on Vdd-plane
It is pretty clear that a solid ground-plane is required for return-
path of I/O-signals. Most people also agree, that a power-plane will
also do this job. But is this only because of the bypass-caps? Or is
the "native" return-current flowing on ground when the output-driver
is sinking and on Vdd when the output-driver is sourcing (assuming a
high-impedance destination), i.e. it would be perfect to have both
planes close to the signal-line?

3. Shields of connectors, chassis ground
Most PCBs have one or more connectors with shields (e.g. USB, RJ45,
VGA, RS-232,...) Do you connect these directly to circuit-ground? Or
with C and R in parallel? Or do you have some kind of "frame-ground"?
Have you the mounting holes grounded to the chassis? All or just one?

Thanks,

Thomas

Hi Thomas,

1) Yes. That will keep noise from coupling between devices.
2) Only nutters have power planes. They use up valuable space in which 
you could more profitably use a ground plane.
3) Bond it all together. Unless you have to have isolation from 
dangerous voltages.

If anyone wants to disagree with this advice, I want a specific, first 
person example where what I suggest is wrong. I don't want to hear what 
some 'guru' told you on a course you paid for. :-)

Symsx.



On 3/25/2010 1:10 AM, Thomas Entner wrote:
> As I think, many FPGA-designers have also to deal with EMC, I hope
> someone can help me here. We have currently some discussions (and
> doubts) regarding EMC-topics. As many people have different opinions
> on this subject, and it is quite hard to objectively verify, I would
> like to ask for some comments about following:
>
> 1. Filtering of IC-supply-voltage
> While it is quite standard to filter e.g. the PLL-supply voltages of a
> FPGA, there are some suggestions to filter the supply-voltage of every
> IC (CPU, FPGA, memory, ...) on the PCB with a ferrite-bead + C.
> (Consequently, this also means that every IC has it's own Vdd-island
> in the power-plane.) Does this work?
>
> 2. Return-path on Vdd-plane
> It is pretty clear that a solid ground-plane is required for return-
> path of I/O-signals. Most people also agree, that a power-plane will
> also do this job. But is this only because of the bypass-caps? Or is
> the "native" return-current flowing on ground when the output-driver
> is sinking and on Vdd when the output-driver is sourcing (assuming a
> high-impedance destination), i.e. it would be perfect to have both
> planes close to the signal-line?
>
> 3. Shields of connectors, chassis ground
> Most PCBs have one or more connectors with shields (e.g. USB, RJ45,
> VGA, RS-232,...) Do you connect these directly to circuit-ground? Or
> with C and R in parallel? Or do you have some kind of "frame-ground"?
> Have you the mounting holes grounded to the chassis? All or just one?
>
> Thanks,
>
> Thomas

On Mar 24, 9:10=A0pm, Thomas Entner <thomas.ent...@entner-
electronics.com> wrote:
> As I think, many FPGA-designers have also to deal with EMC, I hope
> someone can help me here. We have currently some discussions (and
> doubts) regarding EMC-topics. As many people have different opinions
> on this subject, and it is quite hard to objectively verify, I would
> like to ask for some comments about following:
>
> 1. Filtering of IC-supply-voltage
> While it is quite standard to filter e.g. the PLL-supply voltages of a
> FPGA, there are some suggestions to filter the supply-voltage of every
> IC (CPU, FPGA, memory, ...) on the PCB with a ferrite-bead + C.
> (Consequently, this also means that every IC has it's own Vdd-island
> in the power-plane.) Does this work?
>
> 2. Return-path on Vdd-plane
> It is pretty clear that a solid ground-plane is required for return-
> path of I/O-signals. Most people also agree, that a power-plane will
> also do this job. But is this only because of the bypass-caps? Or is
> the "native" return-current flowing on ground when the output-driver
> is sinking and on Vdd when the output-driver is sourcing (assuming a
> high-impedance destination), i.e. it would be perfect to have both
> planes close to the signal-line?
>
> 3. Shields of connectors, chassis ground
> Most PCBs have one or more connectors with shields (e.g. USB, RJ45,
> VGA, RS-232,...) Do you connect these directly to circuit-ground? Or
> with C and R in parallel? Or do you have some kind of "frame-ground"?
> Have you the mounting holes grounded to the chassis? All or just one?
>
> Thanks,
>
> Thomas

1) Filtering independent islands will help pushing VCC noise out to
other chips and provide less of a radiation footprint.  Another
benefit for smaller islands: the resonance of that small section of
board is now *much* higher in frequency.  Having too many islands with
too many signals jumping over the straits between land can create
problems as well.

2) Return path works because of decoupling.  The drivers have to be
well decoupled to work so launching into power or ground referenced
planes has no issue.  Crossing from one plane reference to another -
including changing through vias - needs a decoupling capacitor
*somewhere* nearby to avoid having too large an effective antenna loop
for EMI and crosstalk.  A signal switching from external ground plane
referenced microstrip to an internal ground and power sandwiched
stripline still requires that some of the return current be shared
with the power plane.

If you have signals crossing between planes in the X-Y or the Z
direction, decoupling needs to be nearby.

There's no reason it would be perfect to have both planes nearby.  The
ground still has to share return current with power and vice-versa.
Decoupling on-chip is common as well.  I've seen information that
suggests there's little effect external decoupling has on frequency
content above 30MHz; on-chip resources are needed for those fast
transitions.

3) Shields are one of the nastiest forms of black art.  What we tended
to do for the printers designed at my previous company was include
spots to solder in our choice of resistor (including 0 ohm),
capacitor, or ferrite.  The choice was made during initial EMI scans
but the island was always chassis ground through the metal mounting
plate openings.

I ended up having to do some expensive mechanical/electrical
alterations to a board I did in a company before then because of a
couple millivolts of noise injected into the COAX shield from the
local ground plane.  EMI was not happy.  If I didn't have the
fluctuation on the plane in the first place, things would have been
happier.

On Mar 24, 8:57=A0pm, Symon <symon_bre...@hotmail.com> wrote:
> 2) Only nutters have power planes. They use up valuable space in which
> you could more profitably use a ground plane.

Surely you mean "Only nutters have separately filtered power planes
for individual general purpose digital IC supplies."

Otherwise, suggesting that planes (partial or full) are not needed for
power distribution to digital circuitry is ludicrous.

> If anyone wants to disagree with this advice, I want a specific, first
> person example where what I suggest is wrong. I don't want to hear what
> some 'guru' told you on a course you paid for. :-)

Why should we supply any more evidence than you have?

Andy

Thomas,

Some thoughts:

> 1. Filtering of IC-supply-voltage
> While it is quite standard to filter e.g. the PLL-supply voltages of a
> FPGA, there are some suggestions to filter the supply-voltage of every
> IC (CPU, FPGA, memory, ...) on the PCB with a ferrite-bead + C.
> (Consequently, this also means that every IC has it's own Vdd-island
> in the power-plane.) Does this work?

You must be using a non-Xilinx device:  our requirements are clearly
spelled out in our user's guides.  And, we do not require filtering
the supply to our clock tile PLL in V5, V6, nor S6.

The MGT's do require filtering, and again this is covered in our
user's guides.  If you chose not to follow our guides, then it is up
to you to prove the system meets your requirements.

> 2. Return-path on Vdd-plane
> It is pretty clear that a solid ground-plane is required for return-
> path of I/O-signals. Most people also agree, that a power-plane will
> also do this job. But is this only because of the bypass-caps? Or is
> the "native" return-current flowing on ground when the output-driver
> is sinking and on Vdd when the output-driver is sourcing (assuming a
> high-impedance destination), i.e. it would be perfect to have both
> planes close to the signal-line?

Again, our plane and signal layer, and its stack-up, is clearly
documented.  Our patented "SparseChevron" technique for IO signal
integrity is superb at reducing ground bounce from SSO (simultaneous
switching outputs).

> 3. Shields of connectors, chassis ground
> Most PCBs have one or more connectors with shields (e.g. USB, RJ45,
> VGA, RS-232,...) Do you connect these directly to circuit-ground? Or
> with C and R in parallel? Or do you have some kind of "frame-ground"?
> Have you the mounting holes grounded to the chassis? All or just one?

Ah, now it gets interesting:  you won't find this in any guide!

Commonly the entire enclosure is a Faraday shield, and is considered
the safety ground, or earth ground, and gets connected to the third
wire ground of the power distribution system (cold water pipe ground/
earth ground/ safety ground).

Now, what you do with that safety ground inside the box, with respect
to your common signal ground is up to you.  A good choice is a hard
connection (no RC) at ONE POINT, as close as possible to where the
safety ground enters the enclosure.  Now, if each interface has its
own safety ground/ shield ground, each of these is terminated on the
Faraday enclosure ground, on the OUTSIDE.  Once the connector leads
enter the enclosure, you DO NOT connect the shield to the circuitry
(it is ONLY connected at that one point described earlier).

Signal grounds inside cables terminate on your pcb ground.  If you
have very long cables between boxes, and there may be a safety ground
voltage difference between enclosures, then the signal grounds may be
only connected at one end, or capacitive coupled at both ends, or some
other solution.  If there is as much as 3 volts AC of safety ground
imbalance (not an unusual requirement), signals may have to be large
swing (like RS232), or differential (RS422) which detail how to be
wired to avoid problems with safety ground voltage differences between
boxes.

Imagine a ESD strike of 10 kv:  it travels from your finger, to the
enclosure, and then remains on the outside, wrapping around until it
gets to the safety ground.  Any opening, a joint without a screw more
than 3" (75mm), will allow the sheet of charge from the ESD to enter
the enclosure, race along the inside surface, and cause your pcb to go
stupid.  Be careful about ESD zaps to display indicators, push
buttons, and switches! Often these displays and controls have to
carefully engineered to prevent ESD zaps from entering the enclosure!

Similarly, an ESD zap to a cable should travel to the enclosure, and
hence back to safety ground, never having a reason to enter the
enclosure.

Once you think you did everything right, then testing with a zapper is
the only way to prove you have met your requirement.

If you are building something that has no ESD requirements, it may
still have RFI/EMI requirements.  All the same rules apply (if the
enclosure is properly designed for ESD, it is very likely also the
best RFI/EMI design as well).  If you have no RFI/EMI requirements,
then you are building a toy, and you probably just don't want them to
be returned to the store, so it is still a good idea to do a good job
with ESD and RFI/EMI, but perhaps cutting corners to reduce costs...

Austin

On 3/25/2010 4:03 PM, austin wrote:
> Thomas,
>
> Some thoughts:
>
>> 1. Filtering of IC-supply-voltage
>> While it is quite standard to filter e.g. the PLL-supply voltages of a
>> FPGA, there are some suggestions to filter the supply-voltage of every
>> IC (CPU, FPGA, memory, ...) on the PCB with a ferrite-bead + C.
>> (Consequently, this also means that every IC has it's own Vdd-island
>> in the power-plane.) Does this work?
>
> You must be using a non-Xilinx device:  our requirements are clearly
> spelled out in our user's guides.  And, we do not require filtering
> the supply to our clock tile PLL in V5, V6, nor S6.
>
It's hard to imagine a board without some non-Xilinx devices on it 
somewhere. Some of these devices may need isolation from the noise 
generated by the FPGA. Power islands are a good way to deal with this.
Syms.

On 3/25/2010 2:55 PM, Andy wrote:
> On Mar 24, 8:57 pm, Symon<symon_bre...@hotmail.com>  wrote:
>> 2) Only nutters have power planes. They use up valuable space in which
>> you could more profitably use a ground plane.
>
> Surely you mean "Only nutters have separately filtered power planes
> for individual general purpose digital IC supplies."

I meant what I said. And don't call me Shirley.
>
> Otherwise, suggesting that planes (partial or full) are not needed for
> power distribution to digital circuitry is ludicrous.

In general, and especially in the context of the OP's points about using 
power planes as signal return paths, I contend that power planes on 
digital boards are expensive and a waste of time. Indeed, they can be 
counter productive. There are many power supplies on the board. For 
example, an FPGA may typically have different supplies on different I/O 
banks, plus a core supply, plus an DCM/PLL supply. Would you have a 
plane for every supply? If you use a single PCB layer for two supplies, 
what happens when a signal on an adjacent layer crosses the gap? What 
happens when you want to isolate a device from a noisy supply?
Far simpler to use the power islands mentioned in the OP, and use 
multiple ground planes for return paths.
>
>> If anyone wants to disagree with this advice, I want a specific, first
>> person example where what I suggest is wrong. I don't want to hear what
>> some 'guru' told you on a course you paid for. :-)
>
> Why should we supply any more evidence than you have?
>
Is that the royal 'we'? :-)

> Andy
>
>

I agree that power islands, where required, are OK, but it was not
clear what your original statement was recommending. Under what
circumstances power islands are required is up for debate.

Whether they are used as signal shield layers (for HF return currents)
is dependent up on the application, whether traces can be routed
without crossing between different islands, and whether or not adding
additional layers for additional ground planes is a good trade.

No sir, I'm just part of the common 'we'  (the same group you adressed
as 'anyone'). Are you the Royal Symon?

Andy

On Mar 25, 10:55=A0am, Andy <jonesa...@comcast.net> wrote:
>
> Otherwise, suggesting that planes (partial or full) are not needed for
> power distribution to digital circuitry is ludicrous.

Consider:

Why do we need power planes?  Are we trying to keep the "reference
rails" common between chips to a very high degree like we do with our
ground planes?

Here's an argument: distributed capacitance between the power and
ground planes are effective at the very high frequency end where
decoupling caps start to loose their effectiveness.  Oops!  Decoupling
at those very high frequencies off-chip doesn't appear to have much
effect [guru suggestion] and the larger the plane, the lower the self-
resonant frequency of that plane.  If you have an 11" board, your
quarter wavelength is about 250MHz.  Smaller planes are more effective
at pushing this high end of resonance out of the picture.  Smaller
planes means smaller distributed capacitance.

I can understand the need for power planes in analog or balanced
circuits where the decoupling effects are still prevalent at the
discrete level.  But for chip level?  Maybe not after all.

After my most recent board involvement I'm convinced that power
distribution would become less problematic with power distributed to
small, chip-local islands.  The small islands do help distribute the
decoupling caps over an area, affecting inter-cap resonance issues.

We've come a long way since the wire-wrap days of star configured
power and ground distribution.  But little attention has been paid to
the science behind power distribution.  There are tools that have
become available in recent years to help plan the power distribution
and avoid the troubles with plane resonance or interference between
capacitors.  The tiny islands might be one of the better ways to go.

On 25 Mrz., 02:10, Thomas Entner <thomas.ent...@entner-
electronics.com> wrote:

> 3. Shields of connectors, chassis ground
> Most PCBs have one or more connectors with shields (e.g. USB, RJ45,
> VGA, RS-232,...) Do you connect these directly to circuit-ground? Or
> with C and R in parallel? Or do you have some kind of "frame-ground"?
> Have you the mounting holes grounded to the chassis? All or just one?

The problem with this is, that for high frequencies and lower
frequencies different
setups work well.
That is why you find conflicting design guids for whether ground and
shield should
be connected and where they should be connected.

Kolja