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A few LatticeMico32 questions

Started by Philip Pemberton April 5, 2010
Hi,
It would seem the Lattice Mico32 support forum has gone dead (no posts/
replies since early February), so I'm asking this here in the hope 
there's an lm32 guru somewhere out there...

I've (successfully) ported the LatticeMico32 CPU core to the Altera 
Cyclone II (terASIC DE1 platform, aka Cyclone II FPGA Starter Board). 
Caching seems to work, as do the WISHBONE interfaces (both of them). Now 
I have a few questions about how the thing works.

- When the core is reset with the cache enabled, it takes a few seconds 
(at a 25Hz clock rate) for the CPU to start executing instructions. 
Nothing happens on the address or data buses during this delay, and 
there's nothing about it in the Lattice manuals. Is there a reset 
debounce delay somewhere in the LM32 logic, or is this just the cache 
being cleared on startup?

- The LM32 has separate instruction and data buses -- the "instruction" 
bus is read-only (the Wishbone WE line is tied low and DATA_O is 
ignored). If I was to write to the instruction space, am I right in 
thinking that this write would be sent over the "data" bus?

- It appears there is a way to disable the Instruction WISHBONE bus 
(undefine CFG_IWB_ENABLED), but disabling this causes compile errors in 
lm32_instruction_unit.v ("object wb_data_f is not declared"). Is this 
supposed to work or am I straying into "Dragons Lurketh Here" territory? 
(I wanted to have the CPU push everything over one bus so I didn't need 
any multi-master arbitration logic).

- Does anyone have any example code for a WISHBONE multi-master arbiter? 
Two-masters-into-one-bus sort of thing? I've got address decoding 
working, but my external RAM is single-port, and I get the feeling an 
8MByte dual-port RAM might be "just a bit" expensive.

- Straying close to the realms of "off topic" a bit here... but does 
anyone have an example "LED blink" type program and linker script to 
produce a flat binary for the lm32 (ideally using GNU as / ld)?
I've got what appears to be a working gcc / binutils toolchain (NOT 
Theobroma's ancient, buggy monstrosity they laughably call a "port"), but 
no instructions on what to do next... How *do* you make gcc/as/ld spit 
out a flat binary?


At this point I just want to get the thing blinking LEDs or something; 
I've hand-assembled a "copy switch input to LEDs" test, but assembling 
code by hand is getting boring (although I did do it -- once -- for a 
6502 CPU board that had a monitor ROM but no onboard assembler or HEX 
download function -- "when the only tool you have is a hammer") :)

Thanks,
-- 
Phil.
usenet09@philpem.me.uk
http://www.philpem.me.uk/
If mail bounces, replace 09 with the last two digits of the current year
> - When the core is reset with the cache enabled, it takes a few seconds > (at a 25Hz clock rate) for the CPU to start executing instructions. > Nothing happens on the address or data buses during this delay, and > there's nothing about it in the Lattice manuals. Is there a reset > debounce delay somewhere in the LM32 logic, or is this just the cache > being cleared on startup?
It should take one cycle per cache line to initialise the cache - not several seconds though.
> - The LM32 has separate instruction and data buses -- the "instruction" > bus is read-only (the Wishbone WE line is tied low and DATA_O is > ignored). If I was to write to the instruction space, am I right in > thinking that this write would be sent over the "data" bus?
Yes
> - It appears there is a way to disable the Instruction WISHBONE bus > (undefine CFG_IWB_ENABLED), but disabling this causes compile errors in > lm32_instruction_unit.v ("object wb_data_f is not declared"). Is this > supposed to work or am I straying into "Dragons Lurketh Here" territory? > (I wanted to have the CPU push everything over one bus so I didn't need > any multi-master arbitration logic).
At one point in time you could disable the wishbone interface and just use an EBR for instruction memory. Maybe that is no longer supported.
> - Does anyone have any example code for a WISHBONE multi-master arbiter? > Two-masters-into-one-bus sort of thing? I've got address decoding > working, but my external RAM is single-port, and I get the feeling an > 8MByte dual-port RAM might be "just a bit" expensive.
Can't you use the code that is generated by Mico32's MSB?
> - Straying close to the realms of "off topic" a bit here... but does > anyone have an example "LED blink" type program and linker script to > produce a flat binary for the lm32 (ideally using GNU as / ld)? > I've got what appears to be a working gcc / binutils toolchain (NOT > Theobroma's ancient, buggy monstrosity they laughably call a "port"), but > no instructions on what to do next... How *do* you make gcc/as/ld spit > out a flat binary?
Why do you want flat? Are you sure you just don't want to convert your ELF file to a binary? If so, you can do lm32-elf-objcopy -O binary file.elf file.bin Cheers, Jon
On Tue, 06 Apr 2010 12:45:58 -0700, Jon Beniston wrote:

> It should take one cycle per cache line to initialise the cache - not > several seconds though.
I did have it running on a very slow clock -- it was actually 12.5Hz (as in, 12.5 cycles per second) so I could watch what it was doing in real- time.
> At one point in time you could disable the wishbone interface and just > use an EBR for instruction memory. Maybe that is no longer supported.
Certainly looks that way to me.
>> - Does anyone have any example code for a WISHBONE multi-master >> arbiter? Two-masters-into-one-bus sort of thing? I've got address >> decoding working, but my external RAM is single-port, and I get the >> feeling an 8MByte dual-port RAM might be "just a bit" expensive. > > Can't you use the code that is generated by Mico32's MSB?
MSB seems to use a lot of IP cores that use Lattice-specific synthesizer features or IP cores. Hardly a good thing when you're trying to make it all work on Altera hardware.
> Why do you want flat?
I basically want a binary image I can program into the Flash chip. I've written a linker script which seems to do what I want (for small assembler programs at least). Making it play nice with C will be the next step, then I can look at porting a bootloader across (probably Qi, U-Boot is an unfortunate victim of creeping featurism). The idea was to have a fast SPI Flash chip, some SDRAM, and a small M4K boot-ROM on the FPGA. The SDRAM is mapped at 0x0000_0000, but reads to that area go through a multiplexer. On powerup (or a RESET), the Mico32 reads from the BootROM. That BootROM copies the firmware off the flash chip and into SDRAM, writes to a register (which switches off the BootROM) and does a soft-reset. At the moment, I'm looking for a decent WISHBONE-compliant SDRAM core... preferably one that isn't GPL'd. -- Phil. usenet09@philpem.me.uk http://www.philpem.me.uk/ If mail bounces, replace "09" with the last two digits of the current year.
> I basically want a binary image I can program into the Flash chip.
In that case, you can just convert the ELF to a binary using lm32-elf- objcopy. Jon
Philip Pemberton <usenet09@philpem.me.uk> wrote:
> Hi, > It would seem the Lattice Mico32 support forum has gone dead (no posts/ > replies since early February), so I'm asking this here in the hope > there's an lm32 guru somewhere out there...
It seem that the most (open) work around LM32 takes place with the Milkymist Project: http://www.milkymist.org/ -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------