I'd rather switch than fight!

On Apr 15, 3:12=A0pm, David Brown <da...@westcontrol.removethisbit.com>
wrote:

> Another famous contest involved a C and Ada comparison. =A0It took the Ad=
a
> more than twice as long as the C team to write their code, but it took
> the C team more than ten times as long to debug their code.

Well, this isn't at all the same then.  The Verilog teams got working
designs, and the VHDL teams didn't.

On Apr 15, 2:23=A0pm, Andy <jonesa...@comcast.net> wrote:
> The benefits of a "strongly typed" language, with bounds checks, etc.
> are somewhat different between the first time you write/use the code,
> and the Nth time reuse and revise it. Strong typeing and bounds
> checking let you know quickly the possibly hidden side effects of
> making changes in the code, especially when it may have been a few
> days/weeks/months since the last time you worked with it.

For this usage, a good testbench will catch more bugs and make strong
type and bounds checking redundant.

>
> A long time ago there was a famous contest for designing a simple
> circuit in verilog vs. vhdl to see which language was better. The
> requirements were provided on paper, and the contestents were given an
> hour or two (don't remember how long, but it was certainly not even a
> day), and whoever got the fastest and the smallest (two winners)
> correct synthesized circuit, their chosen language won. Verilog won
> both, and I don't think vhdl even finished.

Contest details here:

http://www.see.ed.ac.uk/~gerard/Teach/Verilog/manual/Example/lrgeEx2/cooley=
.html

> IMHO, they missed the point. Any design that can be completed in a
> couple of hours will necessarily favor the language with the least
> overhead. Unfortunately, two-hour-solvable designs are not
> representative of real life designs, and neither was the contest's
> declared winner.

Well, I think the takeaway is a lot more nuanced than that, but
whatever.  Believe what you will.

> If you just want to hack out the code and get it working by yourself
> for the day, a weakly typed language may be the better choice for you.
> If you need to be able to reuse/revise/update/extend the design over
> time, more strongly typed languages are preferred.

Again, IMHO, a really good testbench will more than make up for any
perceived weaknesses in Verilog in this area.  But you are free to
continue to believe that the language is really helping you.

Regards,
Pat

On Apr 14, 9:45=A0am, David Brown <da...@westcontrol.removethisbit.com>
wrote:

> When I used confluence, my results were far better. =A0It was simpler and
> clearer, and it handles the low-level Verilog or VHDL details
> automatically. =A0You can't accidentally end up with a latch or
> asynchronous logic in your state machines - in fact, it won't let you
> generate latches at all. =A0You don't have registers that are reset in
> simulation and preset in synthesis, because all the Verilog/VHDL
> registers are generated with explicit resets (or presets). =A0You don't
> have problems when mixing signed and unsigned values, because these are
> handled correctly.
>
> I haven't used MyHDL for more than brief tests, but it appears to give a
> similar isolation from the messy low-level details of Verilog and VHDL,
> while (even more than confluence) it gives you higher level features.
> People often compare Verilog to "C", and VHDL to "Ada" - I think they
> both share a lot with assembly language.

It is easy to use MyHDL in "Confluence mode", for example to describe
recursive structures and dataflows. However, conceptually the
languages are completely different.

It is remarkable that most HDLs that are *proposed*, including
Confluence,
have parallel-only semantics. This idea of a "HDL closely matching
hardware" is rediscovered once in a while. However, it seems the
market just doesn't want it. Personally I'm convinced that such HDLs
are not powerful enough for general purpose digital design work.

In this respect, MyHDL is proudly in the VHDL/Verilog camp, with
strong support for sequential descriptions also. That gives you much
more power, but it implies that there is more to learn and to
understand.

For example, with MyHDL you will also have to learn about latch
inference and how to avoid "unwanted latches". However, just like in
VHDL/Verilog there is a much better solution for this than using a
limited HDL: use a clocked process template by default.

Jan

--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

On Apr 15, 10:21=A0pm, Patrick Maupin <pmau...@gmail.com> wrote:

> Well, this isn't at all the same then. =A0The Verilog teams got working
> designs, and the VHDL teams didn't.

It's really about time that this old VHDL-Verilog shootout nonsense
was shown up for the garbage it was.

It was set up by John Cooley many years ago.  It took place in the
US where Verilog predominated, then as now, so there was a much
smaller pool of skilled VHDL users than Veriloggers at the host
event.  At the time, VHDL did indeed lag badly behind in some
respects - the situation with numeric packages was chaotic, and
the design was a (very simple) counter of some kind so anyone
who wasn't fluent with the VHDL numeric packages **as accepted
by the tools in use** was doomed.  And, as Andy pointed out, the
scale of the problem was so tiny that Verilog would always come
out on top - Verilog is definitely faster to write for tiny
designs; you don't need a contest to work that out.

All of this means that the "contest" was little more than a
good way to show how feeble were VHDL's **tools** at that
time.  It wasn't very long before the tool vendors got their
acts together, but the shootout wasn't re-run; instead, it
became part of the folklore.  It was unreliable populist
hokum then, it's out-of-date unreliable hokum now, and I'm
saddened to see it adduced in evidence so many years on.

There's a lot wrong with VHDL, for sure, but a lot right too.
Here's a sampler of a few things that have been in VHDL since
at least 1987:

Added to Verilog in 2001:
- generate
- multi-dimensional arrays
- signed vector arithmetic
- configurations (nasty in both languages!)

Added to SystemVerilog in 2003-2005:
- packages
- structs (a.k.a. records)
- non-trivial data types (e.g. arrays, structs) on ports
- enumeration types
- unresolved signals (compiler errors on multiple drivers)
- non-trivial data types as subprogram arguments
- reference arguments to subprograms
- default values for input arguments
- inquiry functions to determine the dimensionality and
  bounds of an array

May possibly be added to SystemVerilog in 2012:
- parameterized subprograms (like VHDL unconstrained arrays)
- subprogram overloading

Of course, there's also a ton of stuff that Verilog can do
but VHDL can't.  And it's rarely a good idea to judge any
language by a laundry-list of its feature goodies.  But
it is NEVER a good idea to trivialize the discussion.
--
Jonathan Bromley

On Apr 15, 4:58=A0pm, Jonathan Bromley <s...@oxfordbromley.plus.com>
wrote:

> Of course, there's also a ton of stuff that Verilog can do
> but VHDL can't. =A0And it's rarely a good idea to judge any
> language by a laundry-list of its feature goodies.

Agreed completely.

> =A0But it is NEVER a good idea to trivialize the discussion.

Well, you have to talk to others about that.  Somebody else brought up
the stupid Verilog contest, and David, apparently agreeing with some
sentiment there, said:

> Another famous contest involved a C and Ada comparison.  It took the Ada
> more than twice as long as the C team to write their code, but it took
> the C team more than ten times as long to debug their code.

To which the only sane answer was my flippant "it's not the
same" (and, of course the very first thing that's not the same is who
the purported winner was).  I don't think either contest is worth a
hoot, but I do find it interesting that you found it necessary to pen
a long response to my flippant response, yet found it acceptable to
ignore the statement about the C vs. ADA contest.

Regards,
Pat

On Apr 15, 11:30=A0pm, Patrick Maupin <pmau...@gmail.com> wrote:

> I do find it interesting that you found it necessary to pen
> a long response to my flippant response, yet found it acceptable to
> ignore the statement about the C vs. ADA contest.

I try to write on things I know something about :-)

I am painfully familiar with the Cooley Verilog-vs-VHDL nonsense,
but know nothing about that C-Ada contest.

In any case, I wasn't particularly responding to you.  I took an
opportunity to say something I've wanted to say for a long time
about an exceedingly faulty part of the HDL mythology.
--
Jonathan Bromley

On 15 Apr, 22:33, Jan Decaluwe <j...@jandecaluwe.com> wrote:

> For example, with MyHDL you will also have to learn about latch
> inference and how to avoid "unwanted latches". However, just like in
> VHDL/Verilog there is a much better solution for this than using a
> limited HDL: use a clocked process template by default.

:-) In a rather long thread about vhdl Vs verilog, you seem to have
placed your can opener on another tin of worms marked one process
state machines vs two. What you trying to do, crash google's servers?

On 16/04/2010 00:30, Patrick Maupin wrote:
> On Apr 15, 4:58 pm, Jonathan Bromley<s...@oxfordbromley.plus.com>
> wrote:
>
>> Of course, there's also a ton of stuff that Verilog can do
>> but VHDL can't.  And it's rarely a good idea to judge any
>> language by a laundry-list of its feature goodies.
>
> Agreed completely.
>
>>   But it is NEVER a good idea to trivialize the discussion.
>
> Well, you have to talk to others about that.  Somebody else brought up
> the stupid Verilog contest, and David, apparently agreeing with some
> sentiment there, said:
>

I wasn't agreeing with the validity of the Verilog/VHDL contest, 
although I suppose by not saying that, it looked like I agreed with it. 
  It would have been more useful if I'd given a little more detail.  The 
Ada / C contest was over a much longer time scale, using a real-world 
project - and thus is a much more valid contest (though obviously, like 
any test or benchmark, you can't apply it thoughtlessly to other contexts).

It was an indication of where the stronger typing and generally stricter 
compiler and language was demonstrated to give a faster development time 
in a real case.  I can't say whether those results could carry over to a 
comparison between VHDL and Verilog, or how much the results are the 
effect of strong typing.  But since VHDL is often though of as being a 
similar style of language to Ada, and Verilog is similarly compared to 
C, it may be of interest.

I couldn't find references to the study I was thinking of, but I found 
one in a similar vain:

<http://www.adaic.org/whyada/ada-vs-c/cada_art.html#conclusion>

Of course, I haven't scoured the net looking for enough articles to give 
a balanced view here.  So if my comments here are of interest or use to 
anyone, that's great - if not, I'll not complain if you ignore them!

>> Another famous contest involved a C and Ada comparison.  It took the Ada
>> more than twice as long as the C team to write their code, but it took
>> the C team more than ten times as long to debug their code.
>
> To which the only sane answer was my flippant "it's not the
> same" (and, of course the very first thing that's not the same is who
> the purported winner was).  I don't think either contest is worth a
> hoot, but I do find it interesting that you found it necessary to pen
> a long response to my flippant response, yet found it acceptable to
> ignore the statement about the C vs. ADA contest.
>
> Regards,
> Pat

On 15/04/2010 23:27, Patrick Maupin wrote:
> On Apr 15, 2:23 pm, Andy<jonesa...@comcast.net>  wrote:
>> The benefits of a "strongly typed" language, with bounds checks, etc.
>> are somewhat different between the first time you write/use the code,
>> and the Nth time reuse and revise it. Strong typeing and bounds
>> checking let you know quickly the possibly hidden side effects of
>> making changes in the code, especially when it may have been a few
>> days/weeks/months since the last time you worked with it.
>
> For this usage, a good testbench will catch more bugs and make strong
> type and bounds checking redundant.
>

A testbench does not make checks redundant, for two reasons.  First, the 
earlier in the process that you find the mistakes, the better - its 
easier to find the cause of the mistake, and it's faster to find them, 
fix them, and re-compile.

Secondly, a testbench does not check everything.  It is only as good as 
the work put into it, and can be flawed in the same way as the code 
itself.  A testbench's scope for non-trivial projects is always limited 
- it is not practical to test everything.  If you have some code that 
has a counter, your testbench may not go through the entire range of the 
counter - perhaps doing so would take simulation times of years.  Your 
testbench will then not do bounds checking on the counter.

The old joke about Ada is that when you get your code to compile, it's 
ready to ship.  I certainly wouldn't go that far, but testing is 
something you do in cooperation with static checking, not as an alternative.


mvh.,

David

On Apr 14, 10:07=A0pm, glen herrmannsfeldt <g...@ugcs.caltech.edu>
wrote:
> In comp.arch.fpga rickman <gnu...@gmail.com> wrote:
> (snip)
>
> > People say that strong typing catches bugs, but I've never seen any
> > real proof of that. =A0There are all sorts of anecdotal evidence, but
> > nothing concrete. =A0Sure, wearing a seat belt helps to save lives, but
> > at what point do we draw the line? =A0Should we have four point
> > harnesses, helmets, fireproof suits...?
>
> Seatbelts may save lives, but statistically many other safety
> improvements don't. =A0When people know that their car has air bags,
> they compensate and drive less safely. =A0(Corner a little faster, etc.)
> Enough to mostly remove the life saving effect of the air bags.

Are you making this up?  I have never heard that any of the other
added safety features don't save lives overall.  I have heard that
driving a sportier car does allow you to drive more aggressively, but
this is likely not actually the result of any real analysis, but just
an urban myth.  Where did you hear that air bags don't save lives
after considering all?


> It does seem likely that people will let down their guard and
> code more sloppily knowing that the compiler will catch errors.

If you can show me something that shows this, fine, but otherwise this
is just speculation.


> One of my least favorite is the Java check on variable initialization.
> If the compiler can't be sure that it is initialized then it is
> a fatal compilation error. =A0There are just too many cases that
> the compiler can't get right.

I saw a warning the other day that my VHDL signal initialization "is
not synthesizable".  I checked and it was appropriately initialized on
async reset, it was just complaining that I also used an
initialization in the declaration to keep the simulator from giving me
warnings in library functions.  You just can't please everyone!

Then again I had to make a second trip to the customer yesterday
because of an output that got disconnected in a change and I didn't
see the warning in the ocean of warnings and notes that the tools
generate.  Then I spent half an hour going through all of it in detail
and found a second disconnected signal.  Reminds me of the moon
landing where there was a warning about a loss of sync which kept
happening so much it overloaded the guidance computer and they had to
land manually.  TMI!

Rick