HDL Designer from Mentor

Hello,

I'm wondering if anyone wants to offer up their opinion of Mentor's HDL Designer 
series or FPGA Advantage (Designer + simulation&synthesis)?  I recently acquired 
it, but am wondering about the quality of the resulting code.  It looks like it 
might be very easy to produce stuff with it, but does it save time coding in the 
end?

Thanks,
-robert

Robert Abiad wrote:
> 
> Hello,
> 
> I'm wondering if anyone wants to offer up their opinion of Mentor's HDL 
> Designer series or FPGA Advantage (Designer + simulation&synthesis)?  I 
> recently acquired it, but am wondering about the quality of the 
> resulting code.  It looks like it might be very easy to produce stuff 
> with it, but does it save time coding in the end?


It may be usefully for a schematic oriented designer or
someone learning an hdl.

Once you learn an hdl, you may prefer your own
text editor without all the graphical overhead.


       -- Mike Treseler

Robert Abiad wrote:
> 
> Hello,
> 
> I'm wondering if anyone wants to offer up their opinion of Mentor's HDL 
> Designer series or FPGA Advantage (Designer + simulation&synthesis)?  I 
> recently acquired it, but am wondering about the quality of the 
> resulting code.  It looks like it might be very easy to produce stuff 
> with it, but does it save time coding in the end?
> 
> Thanks,
> -robert
> 

Hi Robert,

I am a HDL user from 4 years.
Now, I cannot do design without HDL. From CPLD design to big Virtex-II, 
HDL is the best I found.

Yes you can continue to write your complet VHDL in text in your favorite 
Text Editor, but do you know the hours for the documentation ?
With HDL designer, the documentation is automatic when you designing, 
the documentation is ready to send to your customers (in html treeview 
or other format).
Maybe, the winners of the next year will be in the reuse design 
methodology. HDL is, for me, the first KEY.

Regards,
Laurent Gauch
www.amontec.com

I've been learning to use it for a month or so.. and I think the suggestion
below is rather limited in its thought.  HDL designer is an good tool for
maintaining the libraries and (now) working with VHDL projects.  It gives a
graphical representation of VHDL code and allows the entry of state
diagrams, flow diagrams as well as block diagrams (schematics).  Add a third
party editor like code-writer, and you get a good VHDL entry tool that is
integrated into HDL.. then add modelsim and you've got a good simulator..
and Leonardo or precision and you've got VHDL (and verilog?) compile and
simulate.  We actually went the simplicity / VHDL way as its supposed to be
a better tool.. but I think that's the guy who 'evaluated' the software's
decision as his preference.

I've not noticed a lot of bugs in HDL designer but it does have a few.. it
can be a bit of a pig to set up too.. This has to be the case as we have a
company policy of not installing it to its default directory.. I think it
doesn't like spaces in names.. such as "program files" .. but then again ..
I can only go by how I was told to set it up.  The editor isn't too bad but
is not company policy so It only gets used when HDL hides files with bugs in
them.. hear no evil .. see no evil I think.  The text editor really doesn't
like you editing a file outside it when the text editor is open thou..
killed HDL twice today doing that :-)

It also integrates with visual source safe but hopefully with others cause
using VSS from within HDL designer runs like a dog with no legs.  I've been
told this is VSS's fault not HDL designer.. but everybody blames Microsoft

Modelsim is an expensive piece of crappy software full of bugs that I
couldn't live without.  It certainly speeds up the design process even if it
crashes 3-4 times a day.

I'm sure someone who knows it better will correct me where I'm wrong.. or
mislead .. but no flames please :-)

Simon

"Mike Treseler" <mike.treseler@flukenetworks.com> wrote in message
news:3F4E6D87.6050705@flukenetworks.com...
>
>
> Robert Abiad wrote:
> >
> > Hello,
> >
> > I'm wondering if anyone wants to offer up their opinion of Mentor's HDL
> > Designer series or FPGA Advantage (Designer + simulation&synthesis)?  I
> > recently acquired it, but am wondering about the quality of the
> > resulting code.  It looks like it might be very easy to produce stuff
> > with it, but does it save time coding in the end?
>
>
> It may be usefully for a schematic oriented designer or
> someone learning an hdl.
>
> Once you learn an hdl, you may prefer your own
> text editor without all the graphical overhead.
>
>
>        -- Mike Treseler
>

I have used FPGAdvantage for the past 2-3 years and despite some bugs that
all SW systems have, I am very satisfied.

I use block diagrams for the hierarchy only and use HDL text files edited in
emacs for all behavioural code. The biggest problems with HDL text files
only designs are to understand how all components is connected together.  So
the graphical block diagram is a very good way to navigate in the design.



The code generated from block diagrams is ok, but a few colleagues have
struggled with crappy code generated from state-machine diagrams and flow
charts. Use them with care!



We have integrated HDL designer with ClearCase and that works well.



I have also struggled a bit with bugs in the interfacing between HDL
designer and the synthesis tool. Now I start the synthesis tool stand-alone
with my own scripts. ModelSim works fine though.



When you learn have to use FPGAdvantage  and how you should not use it, you
will be satisfied!



Hakon Lislebo





"Robert Abiad" <abiad@ssl.berkeley.deletethisandaddedu> wrote in message
news:3F4E6463.5030207@ssl.berkeley.deletethisandaddedu...
>
> Hello,
>
> I'm wondering if anyone wants to offer up their opinion of Mentor's HDL
Designer
> series or FPGA Advantage (Designer + simulation&synthesis)?  I recently
acquired
> it, but am wondering about the quality of the resulting code.  It looks
like it
> might be very easy to produce stuff with it, but does it save time coding
in the
> end?
>
> Thanks,
> -robert
>

H&#4294967295;kon Lisleb&#4294967295; <hakon.lislebo@ericsson.no> wrote in message
news:bin51p$7k$1@newstree.wise.edt.ericsson.se...
> I have used FPGAdvantage for the past 2-3 years and despite some bugs that
> all SW systems have, I am very satisfied.
> I use block diagrams for the hierarchy only and use HDL text files edited
in
> emacs for all behavioural code. The biggest problems with HDL text files
> only designs are to understand how all components is connected together.
So
> the graphical block diagram is a very good way to navigate in the design.
> >
> Hakon Lislebo

Hakon,

If just using the tool for top level block diagrams does it offer
any advantages over a top level schematic in Quartus (Altera's
tool)?

The automatically generated documentation in HTML as mentioned
in another post sounds useful.

If you do generate code from state machine diagrams etc does it
comment the resulting source code at all?



Nial Stewart
------------------------------------------------
Nial Stewart Developments Ltd
FPGA and High Speed Digital Design
www.nialstewartdevelopments.co.uk

Nial,
I am not familiar with the Quartus tool so I can not tell you. I use two or
three levels of hierarchy in my designs and the schematichs is also very
handy to disconnect and reconnect signals. Also if you suddenly want to
route a debug signal up several levels to the top.

I dont remember the commenting of the generated state machine code.

HDL designer is a pretty good project manager as well. And you can write
your own pearl plug-ins.


>
> Hakon,
>
> If just using the tool for top level block diagrams does it offer
> any advantages over a top level schematic in Quartus (Altera's
> tool)?
>
> The automatically generated documentation in HTML as mentioned
> in another post sounds useful.
>
> If you do generate code from state machine diagrams etc does it
> comment the resulting source code at all?
>
>
>
> Nial Stewart
> ------------------------------------------------
> Nial Stewart Developments Ltd
> FPGA and High Speed Digital Design
> www.nialstewartdevelopments.co.uk
>
>

At the risk of starting a toolset discussion, I would recommend
www.aldec.com and their ActiveHDL product.

Its mainly a very user friendly simulator (still not perfect, but a lot
friendlier than Modelsim and on a par with its power and speed) but it also
does much of the design entry and state machine generation/ testbench
generation and project management as well.

It also integrates very well with a large number of synthesis tools so that
you never need to leave ActiveHDL to synthesise and then simulate the
finalised P&R product.

I believe you can get a reduced price Altera-only or Xilinx-only version.

My 2 pence worth :) Having used it for real for a year or so. No affiliation
with the company etc. etc.

Paul Baxter


"Robert Abiad" <abiad@ssl.berkeley.deletethisandaddedu> wrote in message
news:3F4E6463.5030207@ssl.berkeley.deletethisandaddedu...
>
> Hello,
>
> I'm wondering if anyone wants to offer up their opinion of Mentor's HDL
Designer
> series or FPGA Advantage (Designer + simulation&synthesis)?  I recently
acquired
> it, but am wondering about the quality of the resulting code.  It looks
like it
> might be very easy to produce stuff with it, but does it save time coding
in the
> end?
>
> Thanks,
> -robert
>

"Paul Baxter" <pauljnospambaxter@hotnospammail.com> wrote in
message news:3f524aa7$0$254$cc9e4d1f@news.dial.pipex.com...

> At the risk of starting a toolset discussion, I would recommend
> www.aldec.com and their ActiveHDL product.
>
> Its mainly a very user friendly simulator (still not perfect, but a lot
> friendlier than Modelsim

Can you explain a bit more please?  I've heard many people say that
Aldec is more "user-friendly", but personally (strictly personally!)
I've always found its project system and its obsessive copying of
files from place to place to be thoroughly confusing.  It makes
life very easy for you if you have just an HDL design and a
single testbench file and no other tools interested in those
source files, but as soon as I try to do anything more complicated
I get hopelessly mired in its bizarre project system.  (By the
way, I always detested the Aldec project machine in the older
Xilinx tools!).

Once again, for emphasis:  this is my personal opinion only;
we're happy to support any simulators for our training
courses and other work; and my experience with Aldec
is fairly limited, whereas I use ModelSim for the majority
of my day-to-day HDL work.  So I'd be delighted to hear from
any Aldec champions out there.
--

Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223                    mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573                           Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

"Jonathan Bromley" <jonathan.bromley@doulos.com> wrote in message
news:biv4fl$17e$1$8300dec7@news.demon.co.uk...
> "Paul Baxter" <pauljnospambaxter@hotnospammail.com> wrote in
> message news:3f524aa7$0$254$cc9e4d1f@news.dial.pipex.com...
>
> > At the risk of starting a toolset discussion, I would recommend
> > www.aldec.com and their ActiveHDL product.
> >
> > Its mainly a very user friendly simulator (still not perfect, but a lot
> > friendlier than Modelsim
>
> Can you explain a bit more please?  I've heard many people say that
> Aldec is more "user-friendly", but personally (strictly personally!)
> I've always found its project system and its obsessive copying of
> files from place to place to be thoroughly confusing.  It makes
> life very easy for you if you have just an HDL design and a
> single testbench file and no other tools interested in those
> source files, but as soon as I try to do anything more complicated
> I get hopelessly mired in its bizarre project system.  (By the
> way, I always detested the Aldec project machine in the older
> Xilinx tools!).

It certainly lays down a few directories for certain activities (such as
synthesis) but I have quite a flexible arrangement of src code in several
sub-dirs and library directories with no problems. It doesn't copy these
files into another directory with the tool chain I have (Altera/Leonardo).
The exception is that constraint files of various types would need copying
(automatically) into the synthesis directory (though it can generate default
ones in place).

I also have had no problems with a hierarchy of testbench files/dirs for my
specific combination of tools but of course each toolset combination will be
different.

As to user-friendliness, its been a year or so since I last looked at
modelsim, but I found its user interface to have a steeper learning curve
than aldecs. Having said that, as you advance, both provide similar advanced
windows and tools. I guess my main comment is that aldec's felt integrated
as one application whereas I always felt modelsim was a collection of
loosely coupled screens that didn't work so well together.

I was probably tainted by being fairly new to a grown-up simulator (Quartus
doesn't really count) and appreciating the integrated approach of aldec.

Although my benchmarks are out of date (18 months ago) when I did evaluate
both, both aldec and Mentor put up a similar speed for a typical mix of
functional and timing simulations. That left user-interface and ease of use
as my deciding factor.

Paul, Small world: 15 miles from Jonathon :)