Re: I'd rather switch than fight!

On Fri, 23 Apr 2010 08:32:48 -0700 (PDT), Jan Decaluwe
<jan@jandecaluwe.com> wrote:
>So this is now already the third post that I devote to explaining
>to two seasoned Verilog designers how a very simple example in
>their favourite language with the ultra-short learning curve
>actually works. I'm beginning to think that Verilog designers
>don't know how to use variables :-)
>

Actually it was mostly a matter of not paying close attention to
something one "knows" would not work. Of course in a clocked process
if a register is not assigned in a path it remembers its value so a
register is inferred and if it's a blocking assignment, its value is
available in the same clock cycle. When one finally puts these
together, your example is "obvious". 
And you're right; personally I don't use variables in this fashion. I
would write the same logic as follows:

if (turnleft) was_turnleft <= 1;
if (turnleft || was_turnleft) do_left turn;

which I think how the synthesizer would generate the logic for your
example.

-- 
Muzaffer Kal

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