confusion with ADC/DAC interface implementation

Hi,
i am confused regarding the ADC/DAC interface implementation on FPGA.
I have read a code where after serialising the input data of 16 bits
in 16 clock cycles, the interface logic loops (in vain?) for another
16 cyles  before serialising the next data. can#t understand why? why
the serialisation of the next data is not done immediately. moreover,
should the serialisation clock rate be 16 higher than the data stream
clock rate? Sorry but i could not find a documentation detailing all
the synchronization mechanism.

cheers :)

On Apr 22, 8:41=A0pm, alk...@yahoo.co.uk wrote:
> Hi,
> i am confused regarding the ADC/DAC interface implementation on FPGA.
> I have read a code where after serialising the input data of 16 bits
> in 16 clock cycles, the interface logic loops (in vain?) for another
> 16 cyles =A0before serialising the next data. can#t understand why?

Because things work as they are designed...not as they are intended.

Do you have a specific question or are you trolling and asking the
group to fathom why some unlisted code that is implemented in an FPGA
either keeps reading from an ADC or keeps writing to a DAC or perhaps
both?

> why
> the serialisation of the next data is not done immediately. moreover,

Thought you just said it tried again, as you say "in vain?"...sounds
immediate to me

> should the serialisation clock rate be 16 higher than the data stream
> clock rate?

If the ADC shifts out 16 bits of data, then yes it would need to be at
least 16 times as fast as you'd like to sample the analog data.

> Sorry but i could not find a documentation detailing all
> the synchronization mechanism.
>

Are you asking the group to find the documentation for you?

What you need is the datasheet for whatever ADC or DAC that you're
talking about.

Try a more informed posting after you've put some though into your
question and provide some actual details of what you don't understand
and you'll likely get better responses.

KJ

On 23 Apr, 02:42, KJ <kkjenni...@sbcglobal.net> wrote:
> On Apr 22, 8:41=A0pm, alk...@yahoo.co.uk wrote:
>
> > Hi,
> > i am confused regarding the ADC/DAC interface implementation on FPGA.
> > I have read a code where after serialising the input data of 16 bits
> > in 16 clock cycles, the interface logic loops (in vain?) for another
> > 16 cyles =A0before serialising the next data. can#t understand why?
>
> Because things work as they are designed...not as they are intended.
>
> Do you have a specific question or are you trolling and asking the
> group to fathom why some unlisted code that is implemented in an FPGA
> either keeps reading from an ADC or keeps writing to a DAC or perhaps
> both?
>
> > why
> > the serialisation of the next data is not done immediately. moreover,
>
> Thought you just said it tried again, as you say "in vain?"...sounds
> immediate to me
>
> > should the serialisation clock rate be 16 higher than the data stream
> > clock rate?
>
> If the ADC shifts out 16 bits of data, then yes it would need to be at
> least 16 times as fast as you'd like to sample the analog data.
>
> > Sorry but i could not find a documentation detailing all
> > the synchronization mechanism.
>
> Are you asking the group to find the documentation for you?
>
> What you need is the datasheet for whatever ADC or DAC that you're
> talking about.
>
> Try a more informed posting after you've put some though into your
> question and provide some actual details of what you don't understand
> and you'll likely get better responses.
>
> KJ

Wow - grouchy this morning. Did someone piss on your cocoa-pops? ;)

alkosd@yahoo.co.uk pisze:
> Hi,
> i am confused regarding the ADC/DAC interface implementation on FPGA.
> I have read a code where after serialising the input data of 16 bits
> in 16 clock cycles, the interface logic loops (in vain?) for another
> 16 cyles  before serialising the next data. can#t understand why? why
> the serialisation of the next data is not done immediately. moreover,
> should the serialisation clock rate be 16 higher than the data stream
> clock rate? Sorry but i could not find a documentation detailing all
> the synchronization mechanism.
> 
> cheers :)

Hi,

Please specify your ADC DAC type.

BR

Adam

<alkosd@yahoo.co.uk> wrote in message 
news:3bf71478-a08c-4165-9af5-98edd3548e89@8g2000yqz.googlegroups.com...
> Hi,
> i am confused regarding the ADC/DAC interface implementation on FPGA.
> I have read a code where after serialising the input data of 16 bits
> in 16 clock cycles, the interface logic loops (in vain?) for another
> 16 cyles  before serialising the next data. can#t understand why?

As suggested by others your question is very vague, however, some SPI ADC have 
the option to stream out the LSB first. In order to do this you first need to 
stream out the MSB_first word and then you can read the LSB_first word (this 
makes perfect sense for a successive approximation ADC). Thus in the LSB case 
you need 2 sets of n-bit clock cycles.

Find the datasheets and (hopefully) all should become clear,

Hans
www.ht-lab.com


> why
> the serialisation of the next data is not done immediately. moreover,
> should the serialisation clock rate be 16 higher than the data stream
> clock rate? Sorry but i could not find a documentation detailing all
> the synchronization mechanism.
>
> cheers :) 

> Find the datasheets and (hopefully) all should become clear,

thank you for the advice. I got the datasheet at last! i'll work on
the details now. thank you again

On Apr 22, 5:41=A0pm, alk...@yahoo.co.uk wrote:
> Hi,
> i am confused regarding the ADC/DAC interface implementation on FPGA.
> I have read a code where after serialising the input data of 16 bits
> in 16 clock cycles, the interface logic loops (in vain?) for another
> 16 cyles =A0before serialising the next data. can#t understand why? why
> the serialisation of the next data is not done immediately. moreover,
> should the serialisation clock rate be 16 higher than the data stream
> clock rate? Sorry but i could not find a documentation detailing all
> the synchronization mechanism.
>
> cheers :)



For details of this, look up a UART in a text book.

Here is a hint in the right direction.
Assume that data (digital or analog) is transmitted between two
devices
at a certain rate, but asynchronously ie: no clock in the interface.
Can the receive clock be the same frequency of the transmit clock?
Assume there is no way to guarantee any relationship between the
two clocks.  In fact, it is common for them to be slightly
different in frequency.

If the sample clock is 16X faster than the transmit, the middle
of a cycle is found when a start indication is found 8 times.
Then capturethe data values once every 16 times (because the
receive clockis 16X faster).  With this slight differences in
frequency
can be tolerated - depending how many samples are taken between
realigning with a start bit.

Good Luck,
Jim
SynthWorks VHDL