BRAM with output register using ram_style attribute

Hello,

 

I'm curious to know if there is a way we could tell the synthesizer to use
registered mode of BRAM when using ram_style "block" attribute.

The registered mode otherwise can be enabled by instantiating a BRAM with
DOA_REG, DOB_REG set to 1 and REGCEA, REGCEB set to '1'.

 

For example, the VHDLcode below infers a BRAM. However, it does not enable
the registered mode. To get around with it, I've added a process which
registers the output wherever this memory is instantiated. This added
register occupies a slice. Is there a way I can tell the synthesizer to use
the register inside of BRAM (that way I could save resources).

 

====
  attribute ram_style        : string;
  attribute ram_style of RAM : signal is "block";

begin

  process (clk)
  begin
    if clk'event and clk = '1' then
      if en = '1' then
        if we = '1' then
          RAM(conv_integer(addr)) <= di;
        end if;
        do                        <= RAM(conv_integer(addr));
      end if;
    end if;
  end process;


end;
=====

Thanks,
Shantesh	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

On May 25, 7:47=A0pm, "shantesh"
<shantesh84@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote:
> Hello,
>
> I'm curious to know if there is a way we could tell the synthesizer to us=
e
> registered mode of BRAM when using ram_style "block" attribute.
>
> The registered mode otherwise can be enabled by instantiating a BRAM with
> DOA_REG, DOB_REG set to 1 and REGCEA, REGCEB set to '1'.
>
> For example, the VHDLcode below infers a BRAM. However, it does not enabl=
e
> the registered mode. To get around with it, I've added a process which
> registers the output wherever this memory is instantiated. This added
> register occupies a slice. Is there a way I can tell the synthesizer to u=
se
> the register inside of BRAM (that way I could save resources).
>
> =3D=3D=3D=3D
> =A0 attribute ram_style =A0 =A0 =A0 =A0: string;
> =A0 attribute ram_style of RAM : signal is "block";
>
> begin
>
> =A0 process (clk)
> =A0 begin
> =A0 =A0 if clk'event and clk =3D '1' then
> =A0 =A0 =A0 if en =3D '1' then
> =A0 =A0 =A0 =A0 if we =3D '1' then
> =A0 =A0 =A0 =A0 =A0 RAM(conv_integer(addr)) <=3D di;
> =A0 =A0 =A0 =A0 end if;
> =A0 =A0 =A0 =A0 do =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0<=3D RA=
M(conv_integer(addr));
> =A0 =A0 =A0 end if;
> =A0 =A0 end if;
> =A0 end process;
>
> end;
> =3D=3D=3D=3D=3D
>
> Thanks,
> Shantesh =A0 =A0 =A0 =A0 =A0
>
> --------------------------------------- =A0 =A0 =A0 =A0
> Posted throughhttp://www.FPGARelated.com

Rather than adding a process, have you tried simply adding a register
stage in the process where the RAM is inferred?  Somethimes
synthesizers understand your intentions better when they're all
together.