Decoupling for Altera Cyclone II 2C8

Hi guys,
I'm designing a PCB for a project of mine (a floppy disc data analyser -- 
see <http://www.discferret.com/>). This will be my first project with an 
FPGA, or at least the first one that's made it as far as actual PCBs 
being made.

I'm using an Altera Cyclone II EP2C8 in TQ144 (144-pin TQFP) package. 
This has a 40MHz external clock (provided by a TTL oscillator module) 
which is multiplied up to 80MHz and down to 32MHz using the internal PLLs. 
There's an 8-bit multiplexed 10MByte/sec bus between the microcontroller 
(a Microchip PIC) and the FPGA.

This bus has 8 data lines, an Address Latch line, and read and write 
control lines. Address data is sent by putting the address on the bus, 
strobing ALE, then data can be sent in the normal manner. I've got auto-
incrementing address counters on the FPGA which reduce the time delays to 
a more sane degree.

Everything is 3.3V LVTTL/LVCMOS, aside from the USB input to the PIC and 
the disc drive control lines (which are 5V open-collector at 1MHz max). 
No LVDS, LVPECL, ECL or anything like that.

I/O routing is probably a non-issue at these frequencies; clock routing 
for the 40MHz master clock may be an issue -- it needs to come out of the 
TTL osc, then go to the CLKIN pin on the PIC and one of the GCK pins on 
the FPGA. Logic dictates that by putting the TTL module dead-centre 
between the PIC and the FPGA, I can keep clock skew to a minimum. Catch 
is, I'm not sure how that will affect the signal integrity.

The board is double-sided, with the whole bottom layer dedicated to a 
ground plane (with the exception of one or two isolated tracks used to 
move things like VCC around).

What I am worried about is decoupling. The old rule I used to hear banded 
about was "add a 0.1uF ceramic capacitor for every VCC/GND pair, and put 
it as near to that pair as you can, ideally within an inch". For the 2C8 
alone, I'd be looking at 22 capacitors to find space for...
Is 0.1uF the ideal value to use here, or would a 0.01uF work better?

Can anyone offer some advice on the subject of decoupling? It seems it's 
a bit of a black art; the folks I've asked seem very reluctant to explain 
it (if they understand it themselves), and much of the reference material 
I've seen is either oversimplified or starts out simple and then turns 
into a horrendous equation-fest that would give a mathematician a 
migraine.

I've also seem SMD ferrite beads -- typically 600 Ohms @ 100MHz -- used 
in series with the PSU, or as part of a "Pi" filter (inductor in series 
with power supply, capacitors to ground on both sides). Is there any 
advantage to adding these?
(I know an EE who adds them to almost every power line -- his reason is 
"my university lecturer swears you need to do this, and they cost less 
than a penny each")

Thanks,
-- 
Phil.
usenet10@philpem.me.uk
http://www.philpem.me.uk/
If mail bounces, replace "10" with the last two digits of the current year

SI-LIST

Philip

It might be worth looking at this Xilinx applications note
http://www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/component_information/xilinx_xapp623_decoupling_caps.pdf.
Very much the same goes for Altera. Some of the techniques are a bit
extreme but worth a read never the less.

A lot depends on layout whether it will work well. I have seen some
customer projects have some real problems using a 2 layer approach. We
have done 2 layer ourselves on our Polmaddie series of boards but
these have relatively small devices fitted and that reduces the
problem. Like you we have used the back layer as gnd and managed
tracks and power on the other layer to achieve the low cost 2 layer
structure. So far at least we have not seen any problems with these
boards but I wouldn't use them for an application that was high
performance.

On capacitors I would use one per positive power pin as a practical
number.

John Adair
Enterpoint Ltd.


On 15 June, 22:32, Philip Pemberton <usene...@philpem.me.uk> wrote:
> Hi guys,
> I'm designing a PCB for a project of mine (a floppy disc data analyser --
> see <http://www.discferret.com/>). This will be my first project with an
> FPGA, or at least the first one that's made it as far as actual PCBs
> being made.
>
> I'm using an Altera Cyclone II EP2C8 in TQ144 (144-pin TQFP) package.
> This has a 40MHz external clock (provided by a TTL oscillator module)
> which is multiplied up to 80MHz and down to 32MHz using the internal PLLs.
> There's an 8-bit multiplexed 10MByte/sec bus between the microcontroller
> (a Microchip PIC) and the FPGA.
>
> This bus has 8 data lines, an Address Latch line, and read and write
> control lines. Address data is sent by putting the address on the bus,
> strobing ALE, then data can be sent in the normal manner. I've got auto-
> incrementing address counters on the FPGA which reduce the time delays to
> a more sane degree.
>
> Everything is 3.3V LVTTL/LVCMOS, aside from the USB input to the PIC and
> the disc drive control lines (which are 5V open-collector at 1MHz max).
> No LVDS, LVPECL, ECL or anything like that.
>
> I/O routing is probably a non-issue at these frequencies; clock routing
> for the 40MHz master clock may be an issue -- it needs to come out of the
> TTL osc, then go to the CLKIN pin on the PIC and one of the GCK pins on
> the FPGA. Logic dictates that by putting the TTL module dead-centre
> between the PIC and the FPGA, I can keep clock skew to a minimum. Catch
> is, I'm not sure how that will affect the signal integrity.
>
> The board is double-sided, with the whole bottom layer dedicated to a
> ground plane (with the exception of one or two isolated tracks used to
> move things like VCC around).
>
> What I am worried about is decoupling. The old rule I used to hear banded
> about was "add a 0.1uF ceramic capacitor for every VCC/GND pair, and put
> it as near to that pair as you can, ideally within an inch". For the 2C8
> alone, I'd be looking at 22 capacitors to find space for...
> Is 0.1uF the ideal value to use here, or would a 0.01uF work better?
>
> Can anyone offer some advice on the subject of decoupling? It seems it's
> a bit of a black art; the folks I've asked seem very reluctant to explain
> it (if they understand it themselves), and much of the reference material
> I've seen is either oversimplified or starts out simple and then turns
> into a horrendous equation-fest that would give a mathematician a
> migraine.
>
> I've also seem SMD ferrite beads -- typically 600 Ohms @ 100MHz -- used
> in series with the PSU, or as part of a "Pi" filter (inductor in series
> with power supply, capacitors to ground on both sides). Is there any
> advantage to adding these?
> (I know an EE who adds them to almost every power line -- his reason is
> "my university lecturer swears you need to do this, and they cost less
> than a penny each")
>
> Thanks,
> --
> Phil.
> usene...@philpem.me.ukhttp://www.philpem.me.uk/
> If mail bounces, replace "10" with the last two digits of the current year

This is a cost/time/risk trade-off.

How many do you expect to make? 10? 1000? million?

The more you make, the more worthwhile it is trying to reduce the number of
ancilliary components.
http://en.wikipedia.org/wiki/Madman_Muntz

If you intend to make only 1 batch, ensure that the PCB part of the design
works properly, unless you like wasting time+money.

	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

On Jun 15, 5:32=A0pm, Philip Pemberton <usene...@philpem.me.uk> wrote:
> Hi guys,
> I'm designing a PCB for a project of mine (a floppy disc data analyser --
> see <http://www.discferret.com/>). This will be my first project with an
> FPGA, or at least the first one that's made it as far as actual PCBs
> being made.
>
> I'm using an Altera Cyclone II EP2C8 in TQ144 (144-pin TQFP) package.
> This has a 40MHz external clock (provided by a TTL oscillator module)
> which is multiplied up to 80MHz and down to 32MHz using the internal PLLs=
.
> There's an 8-bit multiplexed 10MByte/sec bus between the microcontroller
> (a Microchip PIC) and the FPGA.
>
> This bus has 8 data lines, an Address Latch line, and read and write
> control lines. Address data is sent by putting the address on the bus,
> strobing ALE, then data can be sent in the normal manner. I've got auto-
> incrementing address counters on the FPGA which reduce the time delays to
> a more sane degree.
>
> Everything is 3.3V LVTTL/LVCMOS, aside from the USB input to the PIC and
> the disc drive control lines (which are 5V open-collector at 1MHz max).
> No LVDS, LVPECL, ECL or anything like that.
>
> I/O routing is probably a non-issue at these frequencies; clock routing
> for the 40MHz master clock may be an issue -- it needs to come out of the
> TTL osc, then go to the CLKIN pin on the PIC and one of the GCK pins on
> the FPGA. Logic dictates that by putting the TTL module dead-centre
> between the PIC and the FPGA, I can keep clock skew to a minimum. Catch
> is, I'm not sure how that will affect the signal integrity.
>
> The board is double-sided, with the whole bottom layer dedicated to a
> ground plane (with the exception of one or two isolated tracks used to
> move things like VCC around).
>
> What I am worried about is decoupling. The old rule I used to hear banded
> about was "add a 0.1uF ceramic capacitor for every VCC/GND pair, and put
> it as near to that pair as you can, ideally within an inch". For the 2C8
> alone, I'd be looking at 22 capacitors to find space for...
> Is 0.1uF the ideal value to use here, or would a 0.01uF work better?
>
> Can anyone offer some advice on the subject of decoupling? It seems it's
> a bit of a black art; the folks I've asked seem very reluctant to explain
> it (if they understand it themselves), and much of the reference material
> I've seen is either oversimplified or starts out simple and then turns
> into a horrendous equation-fest that would give a mathematician a
> migraine.
>
> I've also seem SMD ferrite beads -- typically 600 Ohms @ 100MHz -- used
> in series with the PSU, or as part of a "Pi" filter (inductor in series
> with power supply, capacitors to ground on both sides). Is there any
> advantage to adding these?
> (I know an EE who adds them to almost every power line -- his reason is
> "my university lecturer swears you need to do this, and they cost less
> than a penny each")
>
> Thanks,
> --
> Phil.
> usene...@philpem.me.ukhttp://www.philpem.me.uk/
> If mail bounces, replace "10" with the last two digits of the current yea=
r

"Finding space for" capacitors really depends on the package.  You
can get 0.1uF in an 0402 package that almost aligns with adjacent
pads of your TQ144 package.  I normally don't add the ferrites except
for supplies that really need to be quiet.  I'm not that familiar
with Altera parts, but for Xilinx parts I only use ferrites in
the lines supplying transceiver power.  If your part has a separate
power pin for PLL's for example you might want to use ferrites
there.  Also don't forget the bulk decoupling, especially on
the internal Vcc supply where a large portion of the power
draw is dynamic.  I've had large designs fail due to insufficent
bulk capacitance, and it's a real pain to find a place to tack
a 1206 sized cap on after the fact.

Good luck on your project,
Gabor