Using std_ulogic at synthesis level

On Jul 23, 7:22=A0pm, Andy Peters <goo...@latke.net> wrote:
> On Jul 22, 9:50=A0am, Rob Gaddi <rga...@technologyhighland.com> wrote:
>
> > What about more complicated cases such as the following
> > inferred RAM, in which the bottom 7 bits of addr can always be used to
> > address the RAM?
>
> > =A0 =A0 =A0if (addr < 128) then
> > =A0 =A0 =A0 =A0 =A0dout <=3D RAM(addr);
> > =A0 =A0 =A0else
> > =A0 =A0 =A0 =A0 =A0dout <=3D (others =3D> '-');
> > =A0 =A0 =A0end if;
>
> Some hand-optimization might be good here:
>
> =A0 =A0 dout <=3D RAM(addr);
>
> After all, in this (likely contrived!) case, you don't care about the
> assignment if the address is 128 or higher, so then not doing the
> comparison at all and just doing the assignment anyway gives the best
> result.
>
> A smart synthesis tool should do that optimization.
>

Not quite.  As I mentioned in my earlier post, the way to write the
code is
dout <=3D ram(addr mod 128);

If you just write "dout <=3D RAM(addr);" then a larger memory will be
inferred.  You're assuming that addr is not something 'big' like

signal addr: natural range 0 to 1048575; -- 20 bits

Kevin Jennings