One issue about free hardware

> With two clocks and two write ports!? 

Ok, maybe not that particular case, but most other configurations of
dual-port RAM can be infered. In Verilog at least, isn't this a
problem with the language rather than the FPGA tools (i.e. you can't
write to the same variable from two different processes)?

> Open-source doesn't *have* to mean no-cost... 

Sure. I was more refering to that fact that due to the quality & size
of some open source/free software projects, the bar has been raised
significantly.

Cheers,
JonB

Tom Hawkins wrote:

> What can we do to improve open-source EDA?
> 
> Regards,
> Tom
> 

For me, and I guess for a lot of people in this industry, contribute to 
open source could be a legal minefield:

- In my job contract, it stated my employer own the copyright of designs 
I done.  So officially I cannot post any IP design/source code to public.

- Patent issues. Some of my knowledge might relate to patented products. 
Release of such information could mean I could get sued.

And of course, usually I am too tired after work anyway ;-)

Joe

jon@beniston.com (Jon Beniston) writes:

> > With two clocks and two write ports!? 
> 
> Ok, maybe not that particular case, but most other configurations of
> dual-port RAM can be infered. In Verilog at least, isn't this a
> problem with the language rather than the FPGA tools (i.e. you can't
> write to the same variable from two different processes)?
> 

:-)  I'm slightly bitter - as that's just what I want to do right
 now...  Coregen is not an option ... Grrr..

In VHDL you could maybe do it with shared variables, but I've always
avoided them to avoid shooting myself in the foot!


> > Open-source doesn't *have* to mean no-cost... 
> 
> Sure. I was more refering to that fact that due to the quality & size
> of some open source/free software projects, the bar has been raised
> significantly.
> 

OK.. I thought you were saying that releasing software as either free
or open-source implies you can't get revenue from it.  There are an
enormous number of people managing it though!

Cheers,
Martin

-- 
martin.j.thompson@trw.com
TRW Conekt, Solihull, UK
http://www.trw.com/conekt

"Joe" <joe_y@invalid_address.nospam.com> wrote in message
news:c7uafp$5cl$1$830fa17d@news.demon.co.uk...
> Tom Hawkins wrote:
>
> > What can we do to improve open-source EDA?
> >
> > Regards,
> > Tom
> >
>
> For me, and I guess for a lot of people in this industry, contribute to
> open source could be a legal minefield:
>
> - In my job contract, it stated my employer own the copyright of designs
> I done.  So officially I cannot post any IP design/source code to public.
>

Depending on the sort of work you do, it can sometimes be directly
economically benificial for your employer if particular code is released as
open source (for example, if you release something that other people will
use and enhance, you get the benifits of their enhancements).  Everything
you write for your employer is owned by them, and in some contracts that
also includes things you write in your own time that are related to your job
(I guess this is some sort of protection against you moonlighting), but if
you want to release some code as open source, you can always ask your
employer for permission.

> - Patent issues. Some of my knowledge might relate to patented products.
> Release of such information could mean I could get sued.

That can be a problem, as can NDAs and other such red tape.

>
> And of course, usually I am too tired after work anyway ;-)

And that is invariably a problem :-(

>
> Joe
>
>
>

jon@beniston.com (Jon Beniston) wrote in message news:<e87b9ce8.0405121132.2e45e653@posting.google.com>...
> > With two clocks and two write ports!? 
> 
> Ok, maybe not that particular case, but most other configurations of
> dual-port RAM can be infered. In Verilog at least, isn't this a
> problem with the language rather than the FPGA tools (i.e. you can't
> write to the same variable from two different processes)?

Verilog does not have this restriction.  I've searched the LRM and
I've run testcases through two reputable implementations without
complaints (ncverilog, icarus).

Hence my frustration.  We can precisely describe a dual port block-ram
in Verilog, yet the tools draw a blank.  We can even preset RAMs with
values, but most, if not all, completely disregard initial statements.

Given the size of their development staff and the prices they are able
to charge, how can they still ignore important parts of the language
standard?

-Tom
 

> 
> > Open-source doesn't *have* to mean no-cost... 
> 
> Sure. I was more refering to that fact that due to the quality & size
> of some open source/free software projects, the bar has been raised
> significantly.
> 
> Cheers,
> JonB

tom1@launchbird.com (Tom Hawkins) writes:

> jon@beniston.com (Jon Beniston) wrote in message news:<e87b9ce8.0405121132.2e45e653@posting.google.com>...
> > > With two clocks and two write ports!? 
> > 
> > Ok, maybe not that particular case, but most other configurations of
> > dual-port RAM can be infered. In Verilog at least, isn't this a
> > problem with the language rather than the FPGA tools (i.e. you can't
> > write to the same variable from two different processes)?
> 
> Verilog does not have this restriction.  I've searched the LRM and
> I've run testcases through two reputable implementations without
> complaints (ncverilog, icarus).
> 
> Hence my frustration.  We can precisely describe a dual port block-ram
> in Verilog, yet the tools draw a blank.  We can even preset RAMs with
> values, but most, if not all, completely disregard initial statements.
> 

I've asked Synplify, and they can infer two-read, one-write, two-clock
RAMs currently.  They plan to support the full two port functionality
in future...

Initials are another thing though!

Cheers,
Martin

-- 
martin.j.thompson@trw.com
TRW Conekt, Solihull, UK
http://www.trw.com/conekt

> > Ok, maybe not that particular case, but most other configurations of
> > dual-port RAM can be infered. In Verilog at least, isn't this a
> > problem with the language rather than the FPGA tools (i.e. you can't
> > write to the same variable from two different processes)?
> 
> Verilog does not have this restriction.  I've searched the LRM and
> I've run testcases through two reputable implementations without
> complaints (ncverilog, icarus).

You are correct. Although it is only ever supported for simulation. I
can kind of understand why though. Take the following:

module test(c1, c2, a, b, d);
input c1, c2, a, b;
output d;
reg d;
always @(posedge c1)
	d <= a;
always @(posedge c2)
	d <= b;
endmodule

What logic would you synthesize it to? Have you tried this with a
behavioural synthesis tool? Maybe that could do a better job.
 
> Hence my frustration.  We can precisely describe a dual port block-ram
> in Verilog, yet the tools draw a blank.  We can even preset RAMs with
> values, but most, if not all, completely disregard initial statements.

Isn't this fixed in v200x? I do agree it's all a bit crap.
 
Cheers,
JonB

Tom Hawkins wrote:

> 2. With Confluence under GPL, I have yet to receive a single bug
> report or source code contribution.
> 

For some tools it can take a very long time to build a userbase.
Step 1. You need to know about it.
        - I know about Confluence.
Step 2. You need to have something suitable to try it with.
        - Maybe this summer...
Step 3. It needs to be good enough.
        No idea... since I have not tried it yet.
Step 4a. It needs to have bugs to give you bug reports :-)
Step 4b. It needs to be incomplete to give you feature requests.
Step 5. Bugs or feature requests that you can't easily fix might
        generate source code contributions.
        Take care when accepting contributions... When added you
        can not dual license (contribution is copyrighted by their author).
        But most contributors won't have a problem with that...

Compare with:
* MySQL
* Qt
* Erlang (functional programming language, GPL:ed by Ericsson) and they have
lots of people internally that uses it.
 - it slowly builds momentum...
But there are a lot more people that use databases, create user
interfaces, ...

/RogerL

-- 
Roger Larsson
Skellefte�
Sweden

>         Take care when accepting contributions... When added you
>         can not dual license (contribution is copyrighted by their author).
>         But most contributors won't have a problem with that...

GCC et al deal with this by requiring contributors to assign
copyright, and it hasn't been a problem for them.
 
> Compare with:
> * MySQL
> * Qt
> * Erlang (functional programming language, GPL:ed by Ericsson) and they have
> lots of people internally that uses it.
>  - it slowly builds momentum...
> But there are a lot more people that use databases, create user
> interfaces, ...

How many FPGA/ASIC designers do we reckon are out there? I'm sure I've
heard Xilinx saying they have a couple hundred thousand installations
of their s/w. That's quite a big target audience.

Cheers,
JonB

Jon Beniston wrote:

> How many FPGA/ASIC designers do we reckon are out there? I'm sure I've
> heard Xilinx saying they have a couple hundred thousand installations
> of their s/w. That's quite a big target audience.

That sounds a little inflated to me.
I would guess only 5-10 thousand in the US.

      -- Mike Treseler