hi, I downloaded the DCT verilog module from the altera website. http://www.altera.com/support/examples/verilog/ver_dct.html I ran a simulation using simple testbench that sends 0,1,2,...63 as the input parameters. The dct_out(output signal) never sends out any result and it always xxxxxx. From the initial basic understanding of the code, the reading the writing of local memory seems done incorrectly. Also the original code has some compilation errors which is given below. Some of the reg needed to be converted to wires to compile. It didn't not seem to alter the functionality. Error (10663): Verilog HDL Port Connection error at dct.v(88): output or inout port "result" must be connected to a structural net expression. Is this IP tested and verified? Thanks regards Shakith
dct verilog
Started by ●August 31, 2010
Reply by ●August 31, 20102010-08-31
Shakes <shakith.fernando@gmail.com> wrote:> I downloaded the DCT verilog module from the altera website. > http://www.altera.com/support/examples/verilog/ver_dct.html> I ran a simulation using simple testbench that sends 0,1,2,...63 as > the input parameters. The dct_out(output signal) never sends out any > result and it always xxxxxx. From the initial basic understanding of > the code, the reading the writing of local memory seems done > incorrectly.I think you can do DCT as a systolic array. I didn't look at the web site to see if that is what it is doing, though. -- glen
Reply by ●August 31, 20102010-08-31
On Aug 31, 9:43=A0pm, Shakes <shakith.ferna...@gmail.com> wrote:> > Is this IP tested and verified? >From the readme file... Contacting Altera =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Although we have made every effort to ensure that this design example works correctly, there might be problems that we have not encountered. If you have a question or problem that is not answered by the information provided in this readme file or the example's documentation, please contact your Altera Field Applications Engineer. If you have additional questions that are not answered in the documentation provided with this function, please contact Altera Applications: World-Wide Web: http://www.altera.com http://www.altera.com/mysupport/ Technical Support Hotline: (800) 800-EPLD (U.S.) (408) 544-7000 (Internationally)
Reply by ●September 2, 20102010-09-02
On Aug 31, 6:43=A0pm, Shakes <shakith.ferna...@gmail.com> wrote: <snippage>> Some of the reg needed to be converted to wires to compile.> Is this IP tested and verified?The statement above answers the question (above). How much testing would you expect to be completed on a module that doesn't compile? RK