Question about OC PCI Cores

Hi, i am using a FPGA PCI board on my project. I was looking at OpenCores
and i found 2 interesting cores. PCI_Bridge and PCI_Target (pci32tlite_oc).


Any one here have any experience with one or both boards? Are they
different on performance? Are they reliable? I was looking on OpenCores
forum and a user was having a problem using PCI_Target on Windows. He had
success to use it on Linux (i will be using on Linux too). He was able to
use PCI_Bridge at both OS with no problem but he wrote that PCI_Bridge is
too slow. PCI_Bridge looks so much complete, whay it would be slower? I was
unconfortable using PCI_Target becouse it is VHDL and PCI_Bridge is
Verilog, and i dont have much experience with VHDL (actualy very little).
So what would you guys sugest me? Any comment about both Cores? 

Thank you!! 	   
					
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On Sep 9, 11:56=A0am, "Sink0" <sink00@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com>
wrote:
> Hi, i am using a FPGA PCI board on my project. I was looking at OpenCores
> and i found 2 interesting cores. PCI_Bridge and PCI_Target (pci32tlite_oc=
).
>
> Any one here have any experience with one or both boards? Are they
> different on performance? Are they reliable? I was looking on OpenCores
> forum and a user was having a problem using PCI_Target on Windows. He had
> success to use it on Linux (i will be using on Linux too). He was able to
> use PCI_Bridge at both OS with no problem but he wrote that PCI_Bridge is
> too slow. PCI_Bridge looks so much complete, whay it would be slower? I w=
as
> unconfortable using PCI_Target becouse it is VHDL and PCI_Bridge is
> Verilog, and i dont have much experience with VHDL (actualy very little).
> So what would you guys sugest me? Any comment about both Cores?
>
> Thank you!! =A0 =A0 =A0 =A0
>
> --------------------------------------- =A0 =A0 =A0 =A0
> Posted throughhttp://www.FPGARelated.com

I don't know for sure, but judging from the names, they do different
things.  A bridge connects two PCI busses.  A target should have PCI
on one side and a different bus on the other to connect to some device
or a function internal to the FPGA.

Which of these do you need?

One of the advantages of open cores is that you can root around in the
guts.  Do you understand how they work?  What software do you expect
to use with them?  The speed issue may be in the software.

Rick

>
>I don't know for sure, but judging from the names, they do different
>things.  A bridge connects two PCI busses.  A target should have PCI
>on one side and a different bus on the other to connect to some device
>or a function internal to the FPGA.
>
>Which of these do you need?
>
>One of the advantages of open cores is that you can root around in the
>guts.  Do you understand how they work?  What software do you expect
>to use with them?  The speed issue may be in the software.
>
>Rick
>

I will be using it on a Spartan-III FPGA. Well not exactly, PCI_Bridge is a
bridge between PCI BUS and Wishbone Bus. But it does have a PCI Master and
PCI Slave module. The PCI Target is a bridge too but as i understood just
have a PCI Slave (and a WB Master on the other hand of the bridge). The
program and drivers are going to be made by me. I will be running on
Linux.	   
					
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"Sink0" <sink00@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote:

>Hi, i am using a FPGA PCI board on my project. I was looking at OpenCores
>and i found 2 interesting cores. PCI_Bridge and PCI_Target (pci32tlite_oc).
>
>
>Any one here have any experience with one or both boards? Are they
>different on performance? Are they reliable? I was looking on OpenCores
>forum and a user was having a problem using PCI_Target on Windows. He had
>success to use it on Linux (i will be using on Linux too). He was able to
>use PCI_Bridge at both OS with no problem but he wrote that PCI_Bridge is
>too slow. PCI_Bridge looks so much complete, whay it would be slower? I was
>unconfortable using PCI_Target becouse it is VHDL and PCI_Bridge is
>Verilog, and i dont have much experience with VHDL (actualy very little).
>So what would you guys sugest me? Any comment about both Cores? 

AFAIK the timing constraints may be the biggest issue besides whether
the core works correct. You should be okay if you make sure the input
and output flipflops are inside the IOBs. You can force the latter
with timing constraints and check it using the floorplanner on the
routed design.

-- 
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico@nctdevpuntnl (punt=.)
--------------------------------------------------------------

On Sep 9, 2:26=A0pm, n...@puntnl.niks (Nico Coesel) wrote:
> "Sink0" <sink00@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote:
> >Hi, i am using a FPGA PCI board on my project. I was looking at OpenCore=
s
> >and i found 2 interesting cores. PCI_Bridge and PCI_Target (pci32tlite_o=
c).
>
> >Any one here have any experience with one or both boards? Are they
> >different on performance? Are they reliable? I was looking on OpenCores
> >forum and a user was having a problem using PCI_Target on Windows. He ha=
d
> >success to use it on Linux (i will be using on Linux too). He was able t=
o
> >use PCI_Bridge at both OS with no problem but he wrote that PCI_Bridge i=
s
> >too slow. PCI_Bridge looks so much complete, whay it would be slower? I =
was
> >unconfortable using PCI_Target becouse it is VHDL and PCI_Bridge is
> >Verilog, and i dont have much experience with VHDL (actualy very little)=
.
> >So what would you guys sugest me? Any comment about both Cores?
>
> AFAIK the timing constraints may be the biggest issue besides whether
> the core works correct. You should be okay if you make sure the input
> and output flipflops are inside the IOBs. You can force the latter
> with timing constraints and check it using the floorplanner on the
> routed design.
>
> --
> Failure does not prove something is impossible, failure simply
> indicates you are not using the right tools...
> nico@nctdevpuntnl (punt=3D.)
> --------------------------------------------------------------

I read a post by someone, likely in this group, about the core they
wrote which was able to clock at 66 MHz while the Xilinx core could
only clock at a little over 33 MHz and needed some careful integration
to do that.  Anyone remember that post?  I think he may have been
discussing his core with Xilinx, I assume because they wanted to
license it.

Rick

> AFAIK the timing constraints may be the biggest issue besides whether
> the core works correct. You should be okay if you make sure the input
> and output flipflops are inside the IOBs. You can force the latter
> with timing constraints and check it using the floorplanner on the
> routed design.


The problem with the PCI interface is that you can't run all the IOs
synchronously. From memory FRAME, TRDY, IRDY and STOP have to be
treated combinatorially at the top level.


Nial. 

"Nial Stewart" <nial*REMOVE_THIS*@nialstewartdevelopments.co.uk>
wrote:

>> AFAIK the timing constraints may be the biggest issue besides whether
>> the core works correct. You should be okay if you make sure the input
>> and output flipflops are inside the IOBs. You can force the latter
>> with timing constraints and check it using the floorplanner on the
>> routed design.
>
>
>The problem with the PCI interface is that you can't run all the IOs
>synchronously. From memory FRAME, TRDY, IRDY and STOP have to be
>treated combinatorially at the top level.

Good question. It shouldn't be difficult to get it properly
constrained. IIRC the Xilinx core also has a bunch of location and
timing constraints to match the PCI specs (which aren't FPGA friendly)
exactly. But my experience with PCI from and FPGA is with Spartan 2
devices.

-- 
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico@nctdevpuntnl (punt=.)
--------------------------------------------------------------

On Sep 10, 4:01=A0pm, n...@puntnl.niks (Nico Coesel) wrote:
> "Nial Stewart" <nial*REMOVE_TH...@nialstewartdevelopments.co.uk>
> wrote:
>
> >> AFAIK the timing constraints may be the biggest issue besides whether
> >> the core works correct. You should be okay if you make sure the input
> >> and output flipflops are inside the IOBs. You can force the latter
> >> with timing constraints and check it using the floorplanner on the
> >> routed design.
>
> >The problem with the PCI interface is that you can't run all the IOs
> >synchronously. From memory FRAME, TRDY, IRDY and STOP have to be
> >treated combinatorially at the top level.
>
> Good question. It shouldn't be difficult to get it properly
> constrained. IIRC the Xilinx core also has a bunch of location and
> timing constraints to match the PCI specs (which aren't FPGA friendly)
> exactly. But my experience with PCI from and FPGA is with Spartan 2
> devices.
>
> --
> Failure does not prove something is impossible, failure simply
> indicates you are not using the right tools...
> nico@nctdevpuntnl (punt=3D.)
> --------------------------------------------------------------

Xilinx cores make use of special features of certain pins on the
device with names
like IRDY and TRDY that have some built-in logic to speed up the
combinatorial
PCI requirements.  I don't think the synthesis tools support these
functions
directly.  However the FPGA's have been getting faster, so you may not
need
the extra stunt hardware to meet PCI timing anymore.

Gabor <gabor@alacron.com> wrote:
> directly.  However the FPGA's have been getting faster, so you may not
> need
> the extra stunt hardware to meet PCI timing anymore.

Clock to output is longer on Spartan-6 than on Spartan-3

Please correct me if I am wrong...
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Very useful information guys. Thank you, but considering that both cores
con work with burst mode and that they are pci complient, so they must be
able to work at 33Mhz, is there any reason for the speed difference? I am
using a Spartan III with Quickswiths for the board. More specificallt
Raggedstone I board made by Enterpoint.

Thank you!	   
					
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