Hi, I am using xiling 9.1 for my design and i am working on 125Mhz system clock. The problem is that i can see the clock on the board and inside FPGA as well but no logic block in my fpga is working. I have no clue about why is it happening because all the timing constraints are met. Kindly give me some pointers, i shall be thankful. Regards Salimbaba --------------------------------------- Posted through http://www.FPGARelated.com
FPGA design not working!
Started by ●October 1, 2010
Reply by ●October 1, 20102010-10-01
On Fri, 01 Oct 2010 05:28:41 -0500, "salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote:>Hi, >I am using xiling 9.1 for my design and i am working on 125Mhz system >clock. The problem is that i can see the clock on the board and inside FPGA >as well but no logic block in my fpga is working. I have no clue about why >is it happening because all the timing constraints are met. Kindly give me >some pointers, i shall be thankful. > > >Regards >Salimbaba > >--------------------------------------- >Posted through http://www.FPGARelated.comHi Salimbaba, I think we need a little more information in order to give a concrete answer. What kind of FPGA are you using, and how are you distributing the clock within the FPGA? Are you using a DCM to instantiate BUFG's, etc? Regards, Kim
Reply by ●October 1, 20102010-10-01
On Oct 1, 6:28=A0am, "salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote:> Hi, > I am using xiling 9.1 for my design and i am working on 125Mhz system > clock. The problem is that i can see the clock on the board and inside FP=GA> as well but no logic block in my fpga is working. I have no clue about wh=y> is it happening because all the timing constraints are met. Kindly give m=e> some pointers, i shall be thankful. >- Did the simulation run correctly? - Did you check that power at the device is correct? - Do you have multiple clocks in your design? - Is this a new board design or a known working board? You've given so little information, that all one can suggest is the basic checks KJ
Reply by ●October 1, 20102010-10-01
o yeah sorry i should've provided you ppl with more info. Well i am using Spartan 3 FPGA (XC3S4000) in my design and it is receiving data from a phy at the clock speed of 125Mhz. I can latch the data at the input which i can see on chipscope, apart from this input signal, i cannot see any other logic block performing. I am not using DCM to instantiate the BUFG's .. i tried that but same problem.>>--------------------------------------- >>Posted through http://www.FPGARelated.com > >Hi Salimbaba, > >I think we need a little more information in order to give a concrete >answer. What kind of FPGA are you using, and how are you distributing >the clock within the FPGA? Are you using a DCM to instantiate BUFG's, >etc? > >Regards, Kim >--------------------------------------- Posted through http://www.FPGARelated.com
Reply by ●October 1, 20102010-10-01
On Fri, 01 Oct 2010 05:28:41 -0500, "salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote:>Hi, >I am using xiling 9.1 for my design and i am working on 125Mhz system >clock. The problem is that i can see the clock on the board and inside FPGA >as well but no logic block in my fpga is working. I have no clue about why >is it happening because all the timing constraints are met. Kindly give me >some pointers, i shall be thankful.Did you simulate your design? Before p&r, after p&r (last resort)? Do you have a reset which is not arriving on hardware? Is clock really arriving into the chip? when you say you can see the clock inside FPGA, what do you mean? Are you forwarding it to a pin which you can probe? -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.com
Reply by ●October 2, 20102010-10-02
"salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote in message news:DqydnWwUoM5EKjjRnZ2dnUVZ_oCdnZ2d@giganews.com...> Hi, > I am using xiling 9.1 for my design and i am working on 125Mhz system > clock. The problem is that i can see the clock on the board and inside > FPGA > as well but no logic block in my fpga is working. I have no clue about why > is it happening because all the timing constraints are met. Kindly give me > some pointers, i shall be thankful.Learn the basics of the fpga editor. Here you can quickly find out if your design has been optimized out for some reason. It is also possible to track signals and add TP's internally with this and just rebuild the bitfile.
Reply by ●October 2, 20102010-10-02
Morten Leikvoll wrote:> Learn the basics of the fpga editor. Here you can quickly find out if your > design has been optimized out for some reason. It is also possible to track > signals and add TP's internally with this and just rebuild the bitfile.I never needed to use a FPGA editor, but it is important to read and understand all the warnings and trying to reduce it to 0 warnings (not always possible, but e.g. in Quartus you can suppress unimportant warnings to see new important ones). -- Frank Buss, http://www.frank-buss.de piano and more: http://www.youtube.com/user/frankbuss
Reply by ●October 2, 20102010-10-02
Frank Buss <fb@frank-buss.de> wrote:>Morten Leikvoll wrote: > >> Learn the basics of the fpga editor. Here you can quickly find out if your >> design has been optimized out for some reason. It is also possible to track >> signals and add TP's internally with this and just rebuild the bitfile. > >I never needed to use a FPGA editor, but it is important to read and >understand all the warnings and trying to reduce it to 0 warnings (not >always possible, but e.g. in Quartus you can suppress unimportant warnings >to see new important ones).I doubt it is possible to have an fpga design without warnings using Xilinx's software. First thing to check is whether the done pin and other programming pins are indicating the configuration is properly loaded. If that is OK I'd create an output signal which is the clock divided by 256 or so to check whether the design is at least doing something. -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------
Reply by ●October 3, 20102010-10-03
>On Oct 1, 6:28=A0am, "salimbaba" ><a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: >> Hi, >> I am using xiling 9.1 for my design and i am working on 125Mhz system >> clock. The problem is that i can see the clock on the board and insideFP=>GA >> as well but no logic block in my fpga is working. I have no clue aboutwh=>y >> is it happening because all the timing constraints are met. Kindly givem=>e >> some pointers, i shall be thankful. >> > >- Did the simulation run correctly? >- Did you check that power at the device is correct? >- Do you have multiple clocks in your design? >- Is this a new board design or a known working board? > >You've given so little information, that all one can suggest is the >basic checks > >KJ >Hi KJ, yeah i successfully simulated the design first and the device power up is also correct. Actually there are 4 clocks coming to the fpga, 2 from ethernet PHY and 2 from oscillators. I am latching the data on the PHY clocks and my whole design is also working on them but i cannot see anything happening =( . and well i have tested this board on 100 Mbps connectivity but now i am testing it on 1Gbps but so far i haven't been able to make it work even a bit. It did work the very first time i programmed it, but when i re-synthesized and reimplemented to make sure it works, it stopped working. Probably different PAR. Any guesses ?any pointers ? Also when i take out some debug signals on Chipscope for debugging purposes, sometimes my design stops working but on removal of those signals it starts working again, do u know its reason ? thanks SalimBaba --------------------------------------- Posted through http://www.FPGARelated.com
Reply by ●October 3, 20102010-10-03
>On Fri, 01 Oct 2010 05:28:41 -0500, "salimbaba" ><a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: > >>Hi, >>I am using xiling 9.1 for my design and i am working on 125Mhz system >>clock. The problem is that i can see the clock on the board and insideFPGA>>as well but no logic block in my fpga is working. I have no clue aboutwhy>>is it happening because all the timing constraints are met. Kindly giveme>>some pointers, i shall be thankful. > >Did you simulate your design? Before p&r, after p&r (last resort)? Do >you have a reset which is not arriving on hardware? Is clock really >arriving into the chip? when you say you can see the clock inside >FPGA, what do you mean? Are you forwarding it to a pin which you can >probe? >-- >Muzaffer Kal > >DSPIA INC. >ASIC/FPGA Design Services >Hi muzaffar, yes i have simulated my design and it works fine. i'll have to see the reset signal,i'll check it tomorrow morning and yes the clock is coming into the chip, i have checked it on Oscilloscope, and i used the data sampling clock as the chipscope master clock so yeah it is coming on chip. and i'll have to confirm the last point by forwarding it to some test point. I'll update it in the morning mate. Thanks a lot =)>http://www.dspia.com >--------------------------------------- Posted through http://www.FPGARelated.com
