Hi, I have a weird problem with my design. I am using xilinx 12.1 for its synthesis and implementation. The problem is that when i generate my bitstream with a chipscope core inserted in the design and program my FPGA, programming fails saying that "DONE did not go high" whereas when i take out the chipscope core or some signals from the core, programming succeeds but after that my JTAG stops working. If i try ti initialize JTAG chain in iMPACT it asks me whether i have a BSDL or BIT file for this device or if i try to run chipscope,it also gives a warning and doesn't start. I checked the JTAG voltages and they were fine. Rarely does my design work, so, i am kind of stuck here as i cannot debug my system altogether. Is there something wrong with the Bit file or my usb drivers? I tried reinstalling the drivers but didn't work. Then i reinstalled xilinx 12.1,still same problem. Does it happen because of the size of the FPGA and the complexity of the logic we are inserting in it ? I mean that if the FPGA is not big enough to hold the logic and it's a very tigh fit, can it lead to such behaviour ? Regards SalimBaba --------------------------------------- Posted through http://www.FPGARelated.com
JTAG stops working!
Started by ●October 11, 2010
Reply by ●October 11, 20102010-10-11
On Oct 11, 3:16=A0pm, "salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote:> Hi, > I have a weird problem with my design. I am using xilinx 12.1 for its > synthesis and implementation. > The problem is that when i generate my bitstream with a chipscope core > inserted in the design and program my FPGA, programming fails saying that > "DONE did not go high" whereas when i take out the chipscope core or some > signals from the core, programming succeeds but after that my JTAG stops > working. If i try ti initialize JTAG chain in iMPACT it asks me whether i > have a BSDL or BIT file for this device or if i try to run chipscope,it > also gives a warning and doesn't start. I checked the JTAG voltages and > they were fine. > > Rarely does my design work, so, i am kind of stuck here as i cannot debug > my system altogether. Is there something wrong with the Bit file or my us=b> drivers? I tried reinstalling the drivers but didn't work. Then i > reinstalled xilinx 12.1,still same problem. > > Does it happen because of the size of the FPGA and the complexity of the > logic we are inserting in it ? I mean that if the FPGA is not big enough =to> hold the logic and it's a very tigh fit, can it lead to such behaviour ? > > Regards > SalimBaba =A0 =A0 =A0 =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.comOne obvious thing that can happen when you put a lot of logic in an FPGA is that the core power supply might not be strong enough to source the required dynamic power. You can get an estimate of the power requirements using Xpower and make sure your power source can handle the current. You can also put an oscilloscope on the Vccint near an FPGA pin or ball, and trigger on a low-going spike. This might either show that your supply cannot handle the current (usually when the spike goes very low or stays low for a long time) or that you have insufficient bypass caps to handle the sudden load increase. Typically right after configuration there is a sudden large rise in Vccint supply current requirement. One thing you might see when the supply cannot handle the load is that the FPGA starts up, gets a glitch in internal power, and then goes back to its power-on reset state due to internal power monitoring. Then the power supply comes back up to voltage because in this state the FPGA again takes much less current. Regards, Gabor
Reply by ●October 12, 20102010-10-12
> >One obvious thing that can happen when you put a lot of logic in an >FPGA >is that the core power supply might not be strong enough to source the >required dynamic power. You can get an estimate of the power >requirements >using Xpower and make sure your power source can handle the current. >You can also put an oscilloscope on the Vccint near an FPGA pin or >ball, >and trigger on a low-going spike. This might either show that your >supply >cannot handle the current (usually when the spike goes very low or >stays >low for a long time) or that you have insufficient bypass caps to >handle >the sudden load increase. Typically right after configuration there >is >a sudden large rise in Vccint supply current requirement. > >One thing you might see when the supply cannot handle the load is >that the FPGA starts up, gets a glitch in internal power, and then >goes back to its power-on reset state due to internal power >monitoring. >Then the power supply comes back up to voltage because in this >state the FPGA again takes much less current. > >Regards, >Gabor >Hi Gabor, I tested the vccint and yeah it goes low when i program the FPGA and my JTAG stops working. But i tested the same design's previous revision on it and it worked perfectly fine. Vccint didn't go low. So i reevaluated my design and well the design that didn't work was hierarchical i.e. i made a partition in it and the design that has worked is Flat design i.e. without partitions. I don't know whether the design is hierarchical or flat matters or not. And well logically the Vccint shouldn't go low. Also i analyzed the design using xPower analyzer and it didn't give me any alarming situation. So can you think of any reason for this behaviour ? --------------------------------------- Posted through http://www.FPGARelated.com
Reply by ●October 12, 20102010-10-12
> >I don't know whether the design is hierarchical or flat matters or not.And>well logically the Vccint shouldn't go low. >Did you increase the amount of logic in the design? More power is usually the result of: - more outputs switching - more flip-flops toggling - faster clocks - clocks driven further around the inside of the chip --------------------------------------- Posted through http://www.FPGARelated.com
Reply by ●October 12, 20102010-10-12
>> >>I don't know whether the design is hierarchical or flat matters or not. >And >>well logically the Vccint shouldn't go low. >> > >Did you increase the amount of logic in the design? > >More power is usually the result of: >- more outputs switching >- more flip-flops toggling >- faster clocks >- clocks driven further around the inside of the chip > > > >---------------------------------------No i didn't. Only changed the design from flat to hierarchical.And my design is running at a clock speed of 125Mhz. My regulator can source upto 2.9A current. i don't think FPGA requires this much current, does it ? --------------------------------------- Posted through http://www.FPGARelated.com
Reply by ●October 12, 20102010-10-12
On Oct 12, 7:29=A0am, "salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote:> >>I don't know whether the design is hierarchical or flat matters or not. > >And > >>well logically the Vccint shouldn't go low. > > >Did you increase the amount of logic in the design? > > >More power is usually the result of: > >- more outputs switching > >- more flip-flops toggling > >- faster clocks > >- clocks driven further around the inside of the chip > > >--------------------------------------- =A0 =A0 =A0 =A0 =A0 =A0 > > No i didn't. Only changed the design from flat to hierarchical.And my > design is running at a clock speed of 125Mhz. > > My regulator can source upto 2.9A current. i don't think FPGA requires th=is> much current, does it ? =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.comWhich FPGA? What is the voltage? A Virtex 5 with its 1V Vccint can use more than 3 amperes if heavily loaded. How much Vccint did Xpower report? How big are your bypass caps on Vccint? Are you sure that when you re-ran the design without hierarchy that you didn't lose your .ucf file associations? Placing the pins randomly can certainly cause power draw problems. Regards, Gabor
Reply by ●October 12, 20102010-10-12
> My regulator can source upto 2.9A current. i don't think FPGA requires > this > much current, does it ?Note, if you are using LDO regulators, some of the fast ones can be very sensitive to noise if implemented bad. I've seen one [LP3966 from National to be specific] stop because of a closeby SMPS got started.
Reply by ●October 12, 20102010-10-12
> >Which FPGA? What is the voltage? A Virtex 5 with its 1V Vccint can >use more >than 3 amperes if heavily loaded. How much Vccint did Xpower report? >How >big are your bypass caps on Vccint? Are you sure that when you re-ran >the >design without hierarchy that you didn't lose your .ucf file >associations? Placing >the pins randomly can certainly cause power draw problems. > >Regards, >Gabor >Hi Gabor, I am using spartan 3 xc3s4000 FPGA and vccint before programming is 1.25V and after programming it drops to 720mv. Xpower reported these things : Supply Source | Supply Voltage | Total Current (mA) | --------------------------------------------------------------------------------------------------------------- | Vccint | 1.20 | 113.80 | Vccaux | 2.50 | 55.00 My bypass cap is 100uF. And yeah i am sure i didn't lose the ucf file. --------------------------------------- Posted through http://www.FPGARelated.com
Reply by ●October 12, 20102010-10-12
On Oct 11, 12:16=A0pm, "salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote:> Hi, > I have a weird problem with my design. I am using xilinx 12.1 for its > synthesis and implementation. > The problem is that when i generate my bitstream with a chipscope core > inserted in the design and program my FPGA, programming fails saying that > "DONE did not go high" whereas when i take out the chipscope core or some > signals from the core, programming succeeds but after that my JTAG stops > working. If i try ti initialize JTAG chain in iMPACT it asks me whether i > have a BSDL or BIT file for this device or if i try to run chipscope,it > also gives a warning and doesn't start. I checked the JTAG voltages and > they were fine. > > Rarely does my design work, so, i am kind of stuck here as i cannot debug > my system altogether. Is there something wrong with the Bit file or my us=b> drivers? I tried reinstalling the drivers but didn't work. Then i > reinstalled xilinx 12.1,still same problem. > > Does it happen because of the size of the FPGA and the complexity of the > logic we are inserting in it ? I mean that if the FPGA is not big enough =to> hold the logic and it's a very tigh fit, can it lead to such behaviour ? > > Regards > SalimBaba =A0 =A0 =A0 =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.comI've seen similar behavior with Spartan 2 and Spartan 3 devices where I have to erase the non-volatile memory, then load the FPGA from that empty bitstream before I can then program the FPGA from the JTAG with the new bitstream. It was bitstream dependent. Some images were no problem, while others with minor changes caused trouble. As others have mentioned it could be power supply related although I never managed to catch the problem. kevin It could be
Reply by ●October 13, 20102010-10-13
On Oct 11, 12:16=A0pm, "salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote:> Hi, > I have a weird problem with my design. I am using xilinx 12.1 for its > synthesis and implementation. > The problem is that when i generate my bitstream with a chipscope core > inserted in the design and program my FPGA, programming fails saying that > "DONE did not go high" whereas when i take out the chipscope core or some > signals from the core, programming succeeds but after that my JTAG stops > working. If i try ti initialize JTAG chain in iMPACT it asks me whether i > have a BSDL or BIT file for this device or if i try to run chipscope,it > also gives a warning and doesn't start. I checked the JTAG voltages and > they were fine. > > Rarely does my design work, so, i am kind of stuck here as i cannot debug > my system altogether. Is there something wrong with the Bit file or my us=b> drivers? I tried reinstalling the drivers but didn't work. Then i > reinstalled xilinx 12.1,still same problem. > > Does it happen because of the size of the FPGA and the complexity of the > logic we are inserting in it ? I mean that if the FPGA is not big enough =to> hold the logic and it's a very tigh fit, can it lead to such behaviour ? > > Regards > SalimBaba =A0 =A0 =A0 =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.comThe OP also has this thread on Xilinx Forums for any interested. http://forums.xilinx.com/t5/Implementation/JTAG-stops-working/td-p/95966 Ed McGettigan -- Xilinx Inc.
