JTAG stops working!

On Oct 11, 12:16=A0pm, "salimbaba"
<a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote:
> Hi,
> I have a weird problem with my design. I am using xilinx 12.1 for its
> synthesis and implementation.
> The problem is that when i generate my bitstream with a chipscope core
> inserted in the design and program my FPGA, programming fails saying that
> "DONE did not go high" whereas when i take out the chipscope core or some
> signals from the core, programming succeeds but after that my JTAG stops
> working. If i try ti initialize JTAG chain in iMPACT it asks me whether i
> have a BSDL or BIT file for this device or if i try to run chipscope,it
> also gives a warning and doesn't start. I checked the JTAG voltages and
> they were fine.
>
> Rarely does my design work, so, i am kind of stuck here as i cannot debug
> my system altogether. Is there something wrong with the Bit file or my us=
b
> drivers? I tried reinstalling the drivers but didn't work. Then i
> reinstalled xilinx 12.1,still same problem.
>
> Does it happen because of the size of the FPGA and the complexity of the
> logic we are inserting in it ? I mean that if the FPGA is not big enough =
to
> hold the logic and it's a very tigh fit, can it lead to such behaviour ?
>
> Regards
> SalimBaba =A0 =A0 =A0 =A0 =A0
>
> --------------------------------------- =A0 =A0 =A0 =A0
> Posted throughhttp://www.FPGARelated.com

I would guess that there's something wrong with your ILA.

RK

On Oct 11, 3:51=A0pm, Gabor <ga...@alacron.com> wrote:
> On Oct 11, 3:16=A0pm, "salimbaba"
>
>
>
> <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote:
> > Hi,
> > I have a weird problem with my design. I am using xilinx 12.1 for its
> > synthesis and implementation.
> > The problem is that when i generate my bitstream with a chipscope core
> > inserted in the design and program my FPGA, programming fails saying th=
at
> > "DONE did not go high" whereas when i take out the chipscope core or so=
me
> > signals from the core, programming succeeds but after that my JTAG stop=
s
> > working. If i try ti initialize JTAG chain in iMPACT it asks me whether=
 i
> > have a BSDL or BIT file for this device or if i try to run chipscope,it
> > also gives a warning and doesn't start. I checked the JTAG voltages and
> > they were fine.
>
> > Rarely does my design work, so, i am kind of stuck here as i cannot deb=
ug
> > my system altogether. Is there something wrong with the Bit file or my =
usb
> > drivers? I tried reinstalling the drivers but didn't work. Then i
> > reinstalled xilinx 12.1,still same problem.
>
> > Does it happen because of the size of the FPGA and the complexity of th=
e
> > logic we are inserting in it ? I mean that if the FPGA is not big enoug=
h to
> > hold the logic and it's a very tigh fit, can it lead to such behaviour =
?
>
> > Regards
> > SalimBaba =A0 =A0 =A0 =A0 =A0
>
> > --------------------------------------- =A0 =A0 =A0 =A0
> > Posted throughhttp://www.FPGARelated.com
>
> One obvious thing that can happen when you put a lot of logic in an
> FPGA
> is that the core power supply might not be strong enough to source the
> required dynamic power. =A0You can get an estimate of the power
> requirements
> using Xpower and make sure your power source can handle the current.
> You can also put an oscilloscope on the Vccint near an FPGA pin or
> ball,
> and trigger on a low-going spike. =A0This might either show that your
> supply
> cannot handle the current (usually when the spike goes very low or
> stays
> low for a long time) or that you have insufficient bypass caps to
> handle
> the sudden load increase. =A0Typically right after configuration there
> is
> a sudden large rise in Vccint supply current requirement.
>
> One thing you might see when the supply cannot handle the load is
> that the FPGA starts up, gets a glitch in internal power, and then
> goes back to its power-on reset state due to internal power
> monitoring.
> Then the power supply comes back up to voltage because in this
> state the FPGA again takes much less current.
>
> Regards,
> Gabor

I've seen this before... I would suggest to turn off all of the clock
sources/ oscillators on  board first to see if the JTAG works any
better ???