using FPGA editor to set IOSTANDARD

I need to add an output pin to my design (virtex6), driven constantly high. 
I've added a new OBUF, OLOGIC, and TIEOFF, and created the routes between 
them.  I have one DRC warning, that the ISTANDARD of the OBUF isn't set.  If 
I look at the properties of the OBUF I see that there is nothing in the 
OSTANDARD parameter.  It should be LVCMOS25.  How do I change it?  It 
doesn't seem to be editable in the properties dialog, and I don't see it in 
the component edit view.

I've already got the change in my RTL for when I run the design next, I just 
want to edit my existing design for now.

thanks,
--steve 

Steve

You need to switch the FPGA Editor into editing mode. Click on
"edirmode" to toggle into editing mode and open the the I/O cell with
"editblock" command. You should set the background set darker
indicating the correct mode and you will be able to set the
properties.

John Adair
Enterpoint Ltd.- Home of Raggedstone2. The Spartan-6 PCIe Development
Board.

On 26 Oct, 18:10, "Steve Ravet" <steve.ra...@arm.com> wrote:
> I need to add an output pin to my design (virtex6), driven constantly hig=
h.
> I've added a new OBUF, OLOGIC, and TIEOFF, and created the routes between
> them. =A0I have one DRC warning, that the ISTANDARD of the OBUF isn't set=
. =A0If
> I look at the properties of the OBUF I see that there is nothing in the
> OSTANDARD parameter. =A0It should be LVCMOS25. =A0How do I change it? =A0=
It
> doesn't seem to be editable in the properties dialog, and I don't see it =
in
> the component edit view.
>
> I've already got the change in my RTL for when I run the design next, I j=
ust
> want to edit my existing design for now.
>
> thanks,
> --steve

Hi John, I've already done that, I had to do it to add the ologic, tieoff, 
and obuf to the design, to create the routing, etc.  When open the IO cell 
for editing in FPGA editor I see checkboxes for PULLTYPE, DIFF_TERM, and 
IBUF_LOW_PWR.  I don't see anything related to IOSTANDARD in the IO cell 
view.

If I right click the OBUF and look at properties, I see the IOSTANDARD on 
the configuration tab, but apparently not editable.  Although I will say 
that FPGA editor in Linux goes have some GUI/mouse/focus issues, so maybe I 
should be able to type into the parameter fields of the properties dialog 
box, and linux/X is preventing it.

thanks,
--steve

"John Adair" <g1@enterpoint.co.uk> wrote in message 
news:c201a335-d459-4eed-8113-a8e3c59ef99b@u10g2000yqk.googlegroups.com...
Steve

You need to switch the FPGA Editor into editing mode. Click on
"edirmode" to toggle into editing mode and open the the I/O cell with
"editblock" command. You should set the background set darker
indicating the correct mode and you will be able to set the
properties.

John Adair
Enterpoint Ltd.- Home of Raggedstone2. The Spartan-6 PCIe Development
Board.

On 26 Oct, 18:10, "Steve Ravet" <steve.ra...@arm.com> wrote:
> I need to add an output pin to my design (virtex6), driven constantly 
> high.
> I've added a new OBUF, OLOGIC, and TIEOFF, and created the routes between
> them. I have one DRC warning, that the ISTANDARD of the OBUF isn't set. If
> I look at the properties of the OBUF I see that there is nothing in the
> OSTANDARD parameter. It should be LVCMOS25. How do I change it? It
> doesn't seem to be editable in the properties dialog, and I don't see it 
> in
> the component edit view.
>
> I've already got the change in my RTL for when I run the design next, I 
> just
> want to edit my existing design for now.
>
> thanks,
> --steve

On Oct 26, 10:58=A0am, "Steve Ravet" <steve.ra...@arm.com> wrote:
> Hi John, I've already done that, I had to do it to add the ologic, tieoff=
,
> and obuf to the design, to create the routing, etc. =A0When open the IO c=
ell
> for editing in FPGA editor I see checkboxes for PULLTYPE, DIFF_TERM, and
> IBUF_LOW_PWR. =A0I don't see anything related to IOSTANDARD in the IO cel=
l
> view.
>
> If I right click the OBUF and look at properties, I see the IOSTANDARD on
> the configuration tab, but apparently not editable. =A0Although I will sa=
y
> that FPGA editor in Linux goes have some GUI/mouse/focus issues, so maybe=
 I
> should be able to type into the parameter fields of the properties dialog
> box, and linux/X is preventing it.
>
> thanks,
> --steve
>
> "John Adair" <g...@enterpoint.co.uk> wrote in message
>
> news:c201a335-d459-4eed-8113-a8e3c59ef99b@u10g2000yqk.googlegroups.com...
> Steve
>
> You need to switch the FPGA Editor into editing mode. Click on
> "edirmode" to toggle into editing mode and open the the I/O cell with
> "editblock" command. You should set the background set darker
> indicating the correct mode and you will be able to set the
> properties.
>
> John Adair
> Enterpoint Ltd.- Home of Raggedstone2. The Spartan-6 PCIe Development
> Board.
>
> On 26 Oct, 18:10, "Steve Ravet" <steve.ra...@arm.com> wrote:
>
>
>
> > I need to add an output pin to my design (virtex6), driven constantly
> > high.
> > I've added a new OBUF, OLOGIC, and TIEOFF, and created the routes betwe=
en
> > them. I have one DRC warning, that the ISTANDARD of the OBUF isn't set.=
 If
> > I look at the properties of the OBUF I see that there is nothing in the
> > OSTANDARD parameter. It should be LVCMOS25. How do I change it? It
> > doesn't seem to be editable in the properties dialog, and I don't see i=
t
> > in
> > the component edit view.
>
> > I've already got the change in my RTL for when I run the design next, I
> > just
> > want to edit my existing design for now.
>
> > thanks,
> > --steve- Hide quoted text -
>
> - Show quoted text -

After you open the OBUF cell using the "Edit Block" button. Click the
"F=3D" icon to add the function/attribute editor and then type in your
desired IO standard into OSTANDARD field.

Ed McGettigan
--
Xilinx Inc.

"Ed McGettigan" <ed.mcgettigan@xilinx.com> wrote in message news:dd44fdde-353d-42f1-ba12-cbd1f5bb154d@30g2000yqm.googlegroups.com...

After you open the OBUF cell using the "Edit Block" button. Click the
"F=" icon to add the function/attribute editor and then type in your
desired IO standard into OSTANDARD field.

Ed McGettigan
--
Xilinx Inc.


Thanks Ed, just what I was looking for.

--steve