I thought this would be easy but I'm having a problem routing one of the wires. I need to create a new output from my fpga, tied high (LX760). What I've done so far: Added a new OBUF H36(and set the OSTANDARD, SLEW, and DRIVE, thanks Ed). Edited the OBUF OUTMUX and OINMUX to create a path from O to the pad. Added a new OLOGIC X0Y318 and created a path from D1 to OQ. Selected OBUF.O and OLOGIC.OQ and created a routed net between them with the add command. Added a new TIEOFF x0Y318. Selected pins TIEOFF.HARD1, OLOGIC.D1,tried to create a routed net between them with the add command but it failed. The specific commands were: select pin VTREF_TIEOFF.HARD1 select pin VTREF_ologic.D1 add The failure message is: ERROR:FPGAEditor:313 - Failed to route net "$NET_1". ERROR:FPGAEditor:316 - Failed to route pin "VTREF_ologic.D1" on net "$NET_1". I've done this kind of thing before, I'm not sure why it isn't working. Any suggestions? thanks, --steve
using FPGA editor to add a new output pin
Started by ●October 27, 2010
Reply by ●October 27, 20102010-10-27
A simpler way might be adding a probe pin if you can find an existing net to attach it to. Yet another possibility is simply enabling a pullup. /Mikhail "Steve Ravet" <steve.ravet@arm.com> wrote in message news:ia9e1k$5gk$1@cam-news1.cambridge.arm.com...>I thought this would be easy but I'm having a problem routing one of the >wires. I need to create a new output from my fpga, tied high (LX760). >What I've done so far: > > Added a new OBUF H36(and set the OSTANDARD, SLEW, and DRIVE, thanks Ed). > Edited the OBUF OUTMUX and OINMUX to create a path from O to the pad. > > Added a new OLOGIC X0Y318 and created a path from D1 to OQ. > > Selected OBUF.O and OLOGIC.OQ and created a routed net between them with > the add command. > > Added a new TIEOFF x0Y318. Selected pins TIEOFF.HARD1, OLOGIC.D1,tried to > create a routed net between them with the add command but it failed. The > specific commands were: > > select pin VTREF_TIEOFF.HARD1 > select pin VTREF_ologic.D1 > add > > The failure message is: > > ERROR:FPGAEditor:313 - Failed to route net "$NET_1". > ERROR:FPGAEditor:316 - Failed to route pin "VTREF_ologic.D1" on net > "$NET_1". > > I've done this kind of thing before, I'm not sure why it isn't working. > Any suggestions? > > thanks, > --steve > > > >
Reply by ●October 27, 20102010-10-27
That's a good idea, to add a probe to the TIEOFF and see how fpga_editor routes it. I just got off the phone with xilinx support, they were able to duplicate the problem. He tried manually routing it as well and was unable to. For now the pullup is exactly what I've done, although I'd like to understand why those pins aren't routable. thanks, --steve "MM" <mbmsv@yahoo.com> wrote in message news:8iqujvF3leU1@mid.individual.net...>A simpler way might be adding a probe pin if you can find an existing net to attach it to. Yet another possibility is simply >enabling a pullup. > > /Mikhail > > > > "Steve Ravet" <steve.ravet@arm.com> wrote in message news:ia9e1k$5gk$1@cam-news1.cambridge.arm.com... >>I thought this would be easy but I'm having a problem routing one of the wires. I need to create a new output from my fpga, tied >>high (LX760). What I've done so far: >> >> Added a new OBUF H36(and set the OSTANDARD, SLEW, and DRIVE, thanks Ed). Edited the OBUF OUTMUX and OINMUX to create a path from >> O to the pad. >> >> Added a new OLOGIC X0Y318 and created a path from D1 to OQ. >> >> Selected OBUF.O and OLOGIC.OQ and created a routed net between them with the add command. >> >> Added a new TIEOFF x0Y318. Selected pins TIEOFF.HARD1, OLOGIC.D1,tried to create a routed net between them with the add command >> but it failed. The specific commands were: >> >> select pin VTREF_TIEOFF.HARD1 >> select pin VTREF_ologic.D1 >> add >> >> The failure message is: >> >> ERROR:FPGAEditor:313 - Failed to route net "$NET_1". >> ERROR:FPGAEditor:316 - Failed to route pin "VTREF_ologic.D1" on net "$NET_1". >> >> I've done this kind of thing before, I'm not sure why it isn't working. Any suggestions? >> >> thanks, >> --steve >> >> >> >> > >
Reply by ●October 27, 20102010-10-27
Steve : FPGA Editor is a great tool to debug and to find synthesis and or implementations tools bugs but never use it as design tool. If you need a new output go back to your HDL add a new output and then go to your UCF to setup the properties to the added output. Never break the implementation tool chain other than to do some simple test. Walter El 2010-10-27 13:53, Steve Ravet escribi�:> That's a good idea, to add a probe to the TIEOFF and see how fpga_editor routes it. I just got off the phone with xilinx support, > they were able to duplicate the problem. He tried manually routing it as well and was unable to. > > For now the pullup is exactly what I've done, although I'd like to understand why those pins aren't routable. > > thanks, > --steve > > "MM"<mbmsv@yahoo.com> wrote in message news:8iqujvF3leU1@mid.individual.net... >> A simpler way might be adding a probe pin if you can find an existing net to attach it to. Yet another possibility is simply >> enabling a pullup. >> >> /Mikhail >> >> >> >> "Steve Ravet"<steve.ravet@arm.com> wrote in message news:ia9e1k$5gk$1@cam-news1.cambridge.arm.com... >>> I thought this would be easy but I'm having a problem routing one of the wires. I need to create a new output from my fpga, tied >>> high (LX760). What I've done so far: >>> >>> Added a new OBUF H36(and set the OSTANDARD, SLEW, and DRIVE, thanks Ed). Edited the OBUF OUTMUX and OINMUX to create a path from >>> O to the pad. >>> >>> Added a new OLOGIC X0Y318 and created a path from D1 to OQ. >>> >>> Selected OBUF.O and OLOGIC.OQ and created a routed net between them with the add command. >>> >>> Added a new TIEOFF x0Y318. Selected pins TIEOFF.HARD1, OLOGIC.D1,tried to create a routed net between them with the add command >>> but it failed. The specific commands were: >>> >>> select pin VTREF_TIEOFF.HARD1 >>> select pin VTREF_ologic.D1 >>> add >>> >>> The failure message is: >>> >>> ERROR:FPGAEditor:313 - Failed to route net "$NET_1". >>> ERROR:FPGAEditor:316 - Failed to route pin "VTREF_ologic.D1" on net "$NET_1". >>> >>> I've done this kind of thing before, I'm not sure why it isn't working. Any suggestions? >>> >>> thanks, >>> --steve >>>--- news://freenews.netfront.net/ - complaints: news@netfront.net ---
Reply by ●October 27, 20102010-10-27
Walter, thanks for the advice. I have already made the change in the RTL but need to press on with this image, and find as many bugs as possible, before spending a week respinning the design. The word back from xilinx support is to not use the TIEOFF, but to instead connect the OBUF.O input to the net GLOBAL_LOGIC1. Did that and it works great. I'd still like to know what the problem was routing the TIEOFF though... --steve "Walter" <wsfpga@adinet.com.uy> wrote in message news:ia9m0j$a9e$1@adenine.netfront.net...> Steve : > > FPGA Editor is a great tool to debug and to find synthesis and or implementations tools bugs but never use it as design tool. > > If you need a new output go back to your HDL add a new output and then go to your UCF to setup the properties to the added output. > > Never break the implementation tool chain other than to do some simple test. > > Walter > > El 2010-10-27 13:53, Steve Ravet escribi�: >> That's a good idea, to add a probe to the TIEOFF and see how fpga_editor routes it. I just got off the phone with xilinx >> support, >> they were able to duplicate the problem. He tried manually routing it as well and was unable to. >> >> For now the pullup is exactly what I've done, although I'd like to understand why those pins aren't routable. >> >> thanks, >> --steve >> >> "MM"<mbmsv@yahoo.com> wrote in message news:8iqujvF3leU1@mid.individual.net... >>> A simpler way might be adding a probe pin if you can find an existing net to attach it to. Yet another possibility is simply >>> enabling a pullup. >>> >>> /Mikhail >>> >>> >>> >>> "Steve Ravet"<steve.ravet@arm.com> wrote in message news:ia9e1k$5gk$1@cam-news1.cambridge.arm.com... >>>> I thought this would be easy but I'm having a problem routing one of the wires. I need to create a new output from my fpga, >>>> tied >>>> high (LX760). What I've done so far: >>>> >>>> Added a new OBUF H36(and set the OSTANDARD, SLEW, and DRIVE, thanks Ed). Edited the OBUF OUTMUX and OINMUX to create a path >>>> from >>>> O to the pad. >>>> >>>> Added a new OLOGIC X0Y318 and created a path from D1 to OQ. >>>> >>>> Selected OBUF.O and OLOGIC.OQ and created a routed net between them with the add command. >>>> >>>> Added a new TIEOFF x0Y318. Selected pins TIEOFF.HARD1, OLOGIC.D1,tried to create a routed net between them with the add >>>> command >>>> but it failed. The specific commands were: >>>> >>>> select pin VTREF_TIEOFF.HARD1 >>>> select pin VTREF_ologic.D1 >>>> add >>>> >>>> The failure message is: >>>> >>>> ERROR:FPGAEditor:313 - Failed to route net "$NET_1". >>>> ERROR:FPGAEditor:316 - Failed to route pin "VTREF_ologic.D1" on net "$NET_1". >>>> >>>> I've done this kind of thing before, I'm not sure why it isn't working. Any suggestions? >>>> >>>> thanks, >>>> --steve >>>> > > > --- news://freenews.netfront.net/ - complaints: news@netfront.net ---
Reply by ●October 28, 20102010-10-28
On Oct 27, 5:48=A0pm, "Steve Ravet" <steve.ra...@arm.com> wrote:> Walter, thanks for the advice. =A0I have already made the change in the R=TL but need to press on with this image, and find as many> bugs as possible, before spending a week respinning the design. > > The word back from xilinx support is to not use the TIEOFF, but to instea=d connect the OBUF.O input to the net GLOBAL_LOGIC1. =A0Did> that and it works great. =A0I'd still like to know what the problem was r=outing the TIEOFF though...> > --steve > > "Walter" <wsf...@adinet.com.uy> wrote in messagenews:ia9m0j$a9e$1@adenine=.netfront.net...> > Steve : > > > FPGA Editor is a great tool to debug and to find synthesis and or imple=mentations tools bugs but never use it as design tool.> > > If you need a new output go back to your HDL add a new output and then =go to your UCF to setup the properties to the added output.> > > Never break the implementation tool chain other than to do some simple =test.> > > Walter > > > El 2010-10-27 13:53, Steve Ravet escribi=F3: > >> That's a good idea, to add a probe to the TIEOFF and see how fpga_edit=or routes it. =A0I just got off the phone with xilinx> >> support, > >> they were able to duplicate the problem. =A0He tried manually routing =it as well and was unable to.> > >> For now the pullup is exactly what I've done, although I'd like to und=erstand why those pins aren't routable.> > >> thanks, > >> --steve > > >> "MM"<mb...@yahoo.com> =A0wrote in messagenews:8iqujvF3leU1@mid.individ=ual.net...> >>> A simpler way might be adding a probe pin if you can find an existing=net to attach it to. Yet another possibility is simply> >>> enabling a pullup. > > >>> /Mikhail > > >>> "Steve Ravet"<steve.ra...@arm.com> =A0wrote in messagenews:ia9e1k$5gk=$1@cam-news1.cambridge.arm.com...> >>>> I thought this would be easy but I'm having a problem routing one of=the wires. =A0I need to create a new output from my fpga,> >>>> tied > >>>> high (LX760). What I've done so far: > > >>>> Added a new OBUF H36(and set the OSTANDARD, SLEW, and DRIVE, thanks =Ed). Edited the OBUF OUTMUX and OINMUX to create a path> >>>> from > >>>> O to the pad. > > >>>> Added a new OLOGIC X0Y318 and created a path from D1 to OQ. > > >>>> Selected OBUF.O and OLOGIC.OQ and created a routed net between them =with the add command.> > >>>> Added a new TIEOFF x0Y318. =A0Selected pins TIEOFF.HARD1, OLOGIC.D1,=tried to create a routed net between them with the add> >>>> command > >>>> but it failed. =A0The specific commands were: > > >>>> select pin VTREF_TIEOFF.HARD1 > >>>> select pin VTREF_ologic.D1 > >>>> add > > >>>> The failure message is: > > >>>> ERROR:FPGAEditor:313 - Failed to route net "$NET_1". > >>>> ERROR:FPGAEditor:316 - Failed to route pin "VTREF_ologic.D1" on net ="$NET_1".> > >>>> I've done this kind of thing before, I'm not sure why it isn't worki=ng. Any suggestions?> > >>>> thanks, > >>>> --steve > > > --- news://freenews.netfront.net/ - complaints: n...@netfront.net ---You might get more clues if you turn on the switch boxes in the FPGA editor view settings. It's possible that the TIEOFF is only accessible for routing to the internal fabric and not the IOB's.
