combinatorial process not simulating correctly

Hi,
I coded a combinatorial process. However when simulated in Modelsim,
the output does not change when my input which is in the process
sensitivity list changes.the output remains constant and takes into
account only the initial value of my input. when i add a clk to my
sensitivity list, i get the expected output. However my process should
be combinatorial! there is nothing wrong with my SIMPLE combinatorial
process. any help please?? I used ISE synthesiser tool to synthesise
my programs .

CHEERS

Angus <angusdundee@googlemail.com> wrote in news:cc605b18-e83d-4ffd-82a9-
6b13ac150ee8@g26g2000vba.googlegroups.com:

> Hi,
> I coded a combinatorial process. However when simulated in Modelsim,
> the output does not change when my input which is in the process
> sensitivity list changes.the output remains constant and takes into
> account only the initial value of my input. when i add a clk to my
> sensitivity list, i get the expected output. However my process should
> be combinatorial! there is nothing wrong with my SIMPLE combinatorial
> process. any help please?? I used ISE synthesiser tool to synthesise
> my programs .
> 
> CHEERS
> 

My crystal ball is broken today, and my extra-sensory perception doesn't seem 
to reach to your location.  :-)    Please provide your code.  All of it.  
Pasted, not re-typed.

I read your posting in comp.arch.fpga, but I am going to guess (since you 
didn't provide much information) that because you also posted to 
comp.lang.vhdl then your code is probably VHDL.  Maybe it is not as SIMPLE 
and as combinatorial as you think.

Thanks!

In comp.arch.fpga Angus <angusdundee@googlemail.com> wrote:

> I coded a combinatorial process. However when simulated in Modelsim,
> the output does not change when my input which is in the process
> sensitivity list changes.

That seems to mean that it isn't combinatorial.

> the output remains constant and takes into
> account only the initial value of my input. when i add a clk to my
> sensitivity list, i get the expected output. 

It shouldn't have a clock, so how can you add one?  

OK, if you add to the sensitivity list and the output changes
when that new signal changes, then it seems that the input is
not in the sensitivity list.   Could it be spelled wrong, so that
it looks like it is in the list?

> However my process should
> be combinatorial! there is nothing wrong with my SIMPLE combinatorial
> process. any help please?? I used ISE synthesiser tool to synthesise
> my programs .

-- glen

all right here you go (I read there was A problem with MODELSIM in
simulating combinatorial processes):

SIGNAL DATA1 : Data_t:=(7,3,2);
SIGNAL DATA2 : Data_t :=(9,5,1);

PROCESS (SEL)
BEGIN
--
         CASE SEL IS
		WHEN "00" =>temp<=DATA1;
		WHEN "01" =>temp<=DATA2;
		WHEN OTHERS =>NULL;
	END CASE;


	Data<=CONV_STD_LOGIC_VECTOR(temp(2),4)&CONV_STD_LOGIC_VECTOR(temp(1),
4)&CONV_STD_LOGIC_VECTOR(temp(0),4);
END PROCESS;
when i change SEL in my testbench, Data does not change. I had to
embed my CASE within a clk edge detection to see the changes on
modelsim

CHEERS

On Nov 5, 7:21=A0am, Angus <angusdun...@googlemail.com> wrote:
> all right here you go (I read there was A problem with MODELSIM in
> simulating combinatorial processes):
>
> SIGNAL DATA1 : Data_t:=3D(7,3,2);
> SIGNAL DATA2 : Data_t :=3D(9,5,1);
>
> PROCESS (SEL)
> BEGIN
> --
> =A0 =A0 =A0 =A0 =A0CASE SEL IS
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN "00" =3D>temp<=3DDATA1;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN "01" =3D>temp<=3DDATA2;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN OTHERS =3D>NULL;
> =A0 =A0 =A0 =A0 END CASE;
>
> =A0 =A0 =A0 =A0 Data<=3DCONV_STD_LOGIC_VECTOR(temp(2),4)&CONV_STD_LOGIC_V=
ECTOR(temp(1),
> 4)&CONV_STD_LOGIC_VECTOR(temp(0),4);
> END PROCESS;
> when i change SEL in my testbench, Data does not change. I had to
> embed my CASE within a clk edge detection to see the changes on
> modelsim
>
> CHEERS
i forgot to add
SIGNAL temp : Data_t ;

On Nov 5, 7:21=A0am, Angus <angusdun...@googlemail.com> wrote:
> all right here you go (I read there was A problem with MODELSIM in
> simulating combinatorial processes):
>
> SIGNAL DATA1 : Data_t:=3D(7,3,2);
> SIGNAL DATA2 : Data_t :=3D(9,5,1);
>
> PROCESS (SEL)
> BEGIN
> --
> =A0 =A0 =A0 =A0 =A0CASE SEL IS
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN "00" =3D>temp<=3DDATA1;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN "01" =3D>temp<=3DDATA2;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN OTHERS =3D>NULL;
> =A0 =A0 =A0 =A0 END CASE;
>
> =A0 =A0 =A0 =A0 Data<=3DCONV_STD_LOGIC_VECTOR(temp(2),4)&CONV_STD_LOGIC_V=
ECTOR(temp(1),
> 4)&CONV_STD_LOGIC_VECTOR(temp(0),4);
> END PROCESS;
> when i change SEL in my testbench, Data does not change. I had to
> embed my CASE within a clk edge detection to see the changes on
> modelsim
>
> CHEERS

obviously,my case statement has 4 conditions, that';s why SEL is of 2
bits. i simplified the code in order not to distract you from the real
problem.

On Nov 5, 8:27=A0am, Angus <angusdun...@googlemail.com> wrote:
> On Nov 5, 7:21=A0am, Angus <angusdun...@googlemail.com> wrote:
>
>
>
> > all right here you go (I read there was A problem with MODELSIM in
> > simulating combinatorial processes):
>
> > SIGNAL DATA1 : Data_t:=3D(7,3,2);
> > SIGNAL DATA2 : Data_t :=3D(9,5,1);
>
> > PROCESS (SEL)
> > BEGIN
> > --
> > =A0 =A0 =A0 =A0 =A0CASE SEL IS
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN "00" =3D>temp<=3DDATA1;
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN "01" =3D>temp<=3DDATA2;
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN OTHERS =3D>NULL;
> > =A0 =A0 =A0 =A0 END CASE;
>
> > =A0 =A0 =A0 =A0 Data<=3DCONV_STD_LOGIC_VECTOR(temp(2),4)&CONV_STD_LOGIC=
_VECTOR(temp(1),
> > 4)&CONV_STD_LOGIC_VECTOR(temp(0),4);
> > END PROCESS;
> > when i change SEL in my testbench, Data does not change. I had to
> > embed my CASE within a clk edge detection to see the changes on
> > modelsim

Your process isn't fully combinatorial: a process in order to be
combinatorial
has to contain in its sensitivity list ALL the inputs that can affect
the output.
In your case you only have the multiplexer selector in the sensitivity
list,
while the DATA1 and DATA2 are not included. Try to add them and it
will
work.

Ciao!
maurizio

On Nov 5, 7:21=A0am, Angus <angusdun...@googlemail.com> wrote:
> all right here you go (I read there was A problem with MODELSIM in
> simulating combinatorial processes):
>
> SIGNAL DATA1 : Data_t:=3D(7,3,2);
> SIGNAL DATA2 : Data_t :=3D(9,5,1);
>
> PROCESS (SEL)
> BEGIN
> --
> =A0 =A0 =A0 =A0 =A0CASE SEL IS
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN "00" =3D>temp<=3DDATA1;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN "01" =3D>temp<=3DDATA2;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN OTHERS =3D>NULL;
> =A0 =A0 =A0 =A0 END CASE;
>
> =A0 =A0 =A0 =A0 Data<=3DCONV_STD_LOGIC_VECTOR(temp(2),4)&CONV_STD_LOGIC_V=
ECTOR(temp(1),
> 4)&CONV_STD_LOGIC_VECTOR(temp(0),4);
> END PROCESS;
> when i change SEL in my testbench, Data does not change. I had to
> embed my CASE within a clk edge detection to see the changes on
> modelsim
>
> CHEERS

As maurizio has pointed out, if you add DATA1 and DATA2 to the
sensitivity list it will work.
But one word of warning - this code will create latches, which is
probably not what you want to do.

> As maurizio has pointed out, if you add DATA1 and DATA2 to the
> sensitivity list it will work.
> But one word of warning - this code will create latches, which is
> probably not what you want to do.

Yes, Tricky, I forgot the latches...sorry for that

Angus, each time in an HDL statement you leave a default behavior that
simply keeps the previous value of a signal (when others => null,
actually
does this) you will introduce a latch element.

A small advice, when you are developing HW, never forget that you are
not writing software, but describing HW. Try to ask yourself "how this
behavior can result in gates?" you will reduce a lot the number of
unwanted behavior.

Good luck!
maurizio

Angus <angusdundee@googlemail.com> writes:

> all right here you go (I read there was A problem with MODELSIM in
> simulating combinatorial processes):
>
> SIGNAL DATA1 : Data_t:=(7,3,2);
> SIGNAL DATA2 : Data_t :=(9,5,1);
>
> PROCESS (SEL)

Do you not want DATA1 and DATA2 in here?  Are you trying to latch your
result *only* when SEL changes (and not when the data changes)?

> BEGIN
> --
>          CASE SEL IS
> 		WHEN "00" =>temp<=DATA1;
> 		WHEN "01" =>temp<=DATA2;
> 		WHEN OTHERS =>NULL;

Here you've scheduled a transaction on temp to happen at the end of
the process.

> 	END CASE;
>
>
> 	Data<=CONV_STD_LOGIC_VECTOR(temp(2),4)&CONV_STD_LOGIC_VECTOR(temp(1),
> 4)&CONV_STD_LOGIC_VECTOR(temp(0),4);

Here you are using temp, but it hasn't updated yet as the process
hasn't suspended.  To get this to update the way you seem to want you
need to use a variable for temp.  That updates immediately.

BTW, you're using conv_std_logic_vector, which means you must have
used ieee.std_logic_arith - don't do that, use ieee.numeric_std.

Some other threads on this:
https://groups.google.com/group/comp.lang.vhdl/browse_thread/thread/389677dd60f7b91c/af0ec67dda4ee7ba?hl=en&ie=UTF-8&q=numeric_std+vs+std_logic_arith&pli=1#af0ec67dda4ee7ba
https://groups.google.com/group/comp.lang.vhdl/browse_thread/thread/549e1bbffd35914d/83cc0f19350fc392?hl=en&ie=UTF-8&q=numeric_std+vs+std_logic_arith#83cc0f19350fc392
http://www.alteraforum.com/forum/showthread.php?t=20925

And some notes I made after writing about it on newsgroups once too often:
http://www.parallelpoints.com/node/3 

> END PROCESS;
> when i change SEL in my testbench, Data does not change. 

Are you sure you're not just seeing it change on the *next* change of sel?

> I had to
> embed my CASE within a clk edge detection to see the changes on
> modelsim

Well, that's probably a good plan anyway, as I doubt the description above is
remotely synthesisable...  That should also show a pipelined behaviour
though (where data changes one extra tick after sel changes).

Cheers,
Martin

-- 
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.co.uk/capabilities/39-electronic-hardware