Brain Cramps...

Geeze!  There are times I wonder how I manage to live without full
time care!  I chased the strangest bug and could not find it to save
my life.  If it had been a snake...

The simulation was exactly what I wanted and I've been doing this a
long time, so I'm not accustomed to the chip not working just like the
simulation.  I downloaded the design and things aren't working like
they should.  The data from the 232 interface was not synching as if
it were not the correct rate.  Putting a probe on the data shows it is
clocking way too fast, a bit is coming out at the rate of the 16x baud
clock!  I brought out several timing strobes they were all over the
map, all two fast, but not even steady.  More like the clock was
glitching all over the place...

To make a long story short... opps, too late for that... I eventually
read the compiler warnings.  I had seen a warning earlier about
finding 9 feedback paths or words to that effect and that didn't quite
wake me up.  It was complaining about the lack of signals in the
sensitivity list of a clocked process... or so I thought.  Instead of
(rising_edge(clk)) I had used ('1' = clk).  Aldec used the sensitivity
list without complaining and so it simulated perfectly.  The real
world saw it differently...  async logic running at top speed!  No
wonder the chip was warmer than usual...

A couple of hours down the drain... yes, a couple of hours!  I kept
adding debug points even though none of them made any sense.

Rick

On 11/23/2010 8:08 AM, rickman wrote:
> Geeze!  There are times I wonder how I manage to live without full
> time care!  I chased the strangest bug and could not find it to save
> my life.  If it had been a snake...
>
 > [snip]
>
> A couple of hours down the drain... yes, a couple of hours!  I kept
> adding debug points even though none of them made any sense.
>
> Rick

There's a lesson to be learned from all that, Rick, but I'll be damned 
if I know what it is.

-- 
Rob Gaddi, Highland Technology
Email address is currently out of order

On Nov 23, 12:08=A0pm, Rob Gaddi <rga...@technologyhighland.com> wrote:
> On 11/23/2010 8:08 AM, rickman wrote:
>
> > Geeze! =A0There are times I wonder how I manage to live without full
> > time care! =A0I chased the strangest bug and could not find it to save
> > my life. =A0If it had been a snake...
>
> =A0> [snip]
>
> > A couple of hours down the drain... yes, a couple of hours! =A0I kept
> > adding debug points even though none of them made any sense.
>
> > Rick
>
> There's a lesson to be learned from all that, Rick, but I'll be damned
> if I know what it is.

Don't program in your sleep!  Did I mention that much of this was done
very late?

Rick

> Instead of (rising_edge(clk)) I had used ('1' = clk).


Do you type in all your code?

I have a template set up so Ctrl-P inserts a 'standard' synchronous process
to save time and cut down this sort of problem.


Nial. 

On Nov 24, 6:15=A0am, "Nial Stewart"
<nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote:
> > Instead of (rising_edge(clk)) I had used ('1' =3D clk).
>
> Do you type in all your code?
>
> I have a template set up so Ctrl-P inserts a 'standard' synchronous proce=
ss
> to save time and cut down this sort of problem.

I wish I had a smart(er) editor that understood VHDL a bit more.  I
have some search/replace regex strings I copy and paste from one file
to another which change an entity port list into a port map or a
signal list.  This helps with the tedium of instantiation.

I've never worried about the sync process before because I haven't
made a mistake like this without it showing up in the simulation.
That is the interesting part.  With the way a simulation works,
comparing the clock to '1' gives exactly the same results as
rising_edge.  Given the function of the sensitivity list, it seems
like the rising_edge function should be redundant.  I believe it
includes some logic to only return true if the preceding state was a
'0' or 'L' rather than just any other value than '1'.  I suppose a =3D
'1' simulation would not work the same triggering on a change from 'H'
to '1' as well as the others.

I'm not likely to forget this and even if I make the same mistake,
I'll likely catch it when I check the compile warnings...

But to answer your question, no, I use CodeWright and I could define
some macro to copy some text into the code, but it wouldn't be at the
correct indentation level.  To do that would require getting to know
CodeWright far too well.  I keep saying some day I'll look into
switching to... (insert your favorite editor here).  I think EMACS is
the one I've heard the most about.

Rick

On Wed, 24 Nov 2010 11:22:33 -0800 (PST), rickman wrote:

> Instead of (rising_edge(clk)) I had used ('1' = clk).
...
>With the way a simulation works,
>comparing the clock to '1' gives exactly the same results as
>rising_edge.  Given the function of the sensitivity list, it seems
>like the rising_edge function should be redundant.

BE CAREFUL!

If there was no asynch reset in your process, then what probably
happened was that the tool saw
  process (clock) begin if clock='1' then...
Not recognizing a standard clocked process, the tool would 
then assume it had a combinational process.  Betcha there
was a warning somewhere in the synth report about automatically
completing the incomplete sensitivity list.  Consequently you
got a pile of transparent latches, enabled (made transparent)
by clock='1'.

On the other hand...

If you have an asynch reset in your sensitivity list, it is
simply not true that rising_edge is redundant.

Consider
  process (clock, reset) begin
    if (reset = '1' then
      do-reset-ish-things;
    elsif clock = '1' then
      do-clocked-things;
    end if;
  end process;

Suppose clock is held at '1', with no edges, and you take
reset from true to false.  The process trips, reset='0' so
the reset action doesn't happen, clock='1' so the clocked
action DOES happen.  Bzzzt! you got a spurious extra clock
action on the trailing edge of reset.

That is why the old-fashioned (pre std_logic_1164) style
of VHDL clocked process, still seen in some dinosaur code
today, looks like this:

  process (clock, reset) begin
    if (reset = '1' then
      do-reset-ish-things;
    elsif clock'event and (clock = '1') then
      do-clocked-things;
    end if;
  end process;

Note the extra clock'event test!  The rising_edge
function includes exactly this test.

This is also the reason why Verilog clocked process
sensitivity lists look like

  always @(posedge clock or posedge reset)

The "posedge reset" often mystifies beginners - hey,
it's a level-sensitive reset, isn't it? - but exactly
the same problem arises of a spurious clock action in
simulation on the trailing edge of reset.  Indeed, it's
even worse in Verilog because you don't test the clock
level (posedge did that for you!) so the spurious action
occurs regardless of the value of clock.

Many synth tools will simply choke on any non-standard
form of clocked process; your tool evidently made the
best it could of it, with appropriately disastrous results.

Sorry to hear about your wasted time.  Sounds to me like 
a good argument for tools NOT to complete the sensitivity
list automatically when they think they've found a
combinational process.
-- 
Jonathan Bromley

On Nov 24, 8:22=A0pm, rickman <gnu...@gmail.com> wrote:
>
> I wish I had a smart(er) editor that understood VHDL a bit more.

Hi Rick,

You might want to take a look at Sigasi: http://www.sigasi.com
We have a VHDL development environment with a VHDL parser inside. This
way, as you put it, the VHDL editor "understands" what you type.

> I have some search/replace regex strings I copy and paste from one file
> to another which change an entity port list into a port map or a
> signal list. =A0This helps with the tedium of instantiation.

Thirty second screencast on instantiations:
http://www.sigasi.com/screencast/entity-instantiation

kind regards

--
Philippe Faes
Sigasi

Philippe <philippe.faes@gmail.com> writes:

> On Nov 24, 8:22&#4294967295;pm, rickman <gnu...@gmail.com> wrote:
>>
>> I wish I had a smart(er) editor that understood VHDL a bit more.
>
> Hi Rick,
>
> You might want to take a look at Sigasi: http://www.sigasi.com

Seconded... Although I haven't bought a license (sorry Philippe!), as
during my eval, I still kept ending up back in Emacs, I will be
recommending it to my "less text-based" colleagues :)

And I may still get one for myself for the refactoring tools.

Cheers,
Martin

-- 
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.co.uk/capabilities/39-electronic-hardware

On Nov 25, 5:26=A0am, Philippe <philippe.f...@gmail.com> wrote:
> On Nov 24, 8:22=A0pm, rickman <gnu...@gmail.com> wrote:
>
>
>
> > I wish I had a smart(er) editor that understood VHDL a bit more.
>
> Hi Rick,
>
> You might want to take a look at Sigasi:http://www.sigasi.com
> We have a VHDL development environment with a VHDL parser inside. This
> way, as you put it, the VHDL editor "understands" what you type.
>
> > I have some search/replace regex strings I copy and paste from one file
> > to another which change an entity port list into a port map or a
> > signal list. =A0This helps with the tedium of instantiation.
>
> Thirty second screencast on instantiations:http://www.sigasi.com/screenca=
st/entity-instantiation
>
> kind regards
>
> --
> Philippe Faes
> Sigasi

To what extent does the editor "understand" the VHDL I type?  I am
already using an editor that recognizes keywords, comments, numbers,
ect... and colors them as I require.  What more does the Sigasi editor
do?

Rick

About Sigasi, rickman <gnuarm@gmail.com> writes:

> To what extent does the editor "understand" the VHDL I type?  I am
> already using an editor that recognizes keywords, comments, numbers,
> ect... and colors them as I require.  What more does the Sigasi editor
> do?
>

It understands the structure of the design - what instantiates what,
what calls what functions.

For example if you rename a port entry on an entity, it can go through
the design changing all the instances of that entity to match.  You
*can* do this with careful use of global search/replace, but this
"just works"

Another example: you can take a process within the entity you're
working on and say "make me an entity of this process", which it will
do, putting the IO in and instantiating it where the process used to
be.  This involves much more than just "matching keywords".

Get the eval and have a play :)

(BTW, although I may sound like a salesman, I have no connection with
Sigasi, other than being impressed with the demo :) I still haven't
quite been torn away from Emacs vhdl-mode though... even though it's
missing the two features above!

Cheers,
Martin

-- 
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.co.uk/capabilities/39-electronic-hardware