Interconnection of multiple cores

Hi,

I have a design in which I use multiple cores for connecting to different
interfaces: SPI, I2C, UART, etc. Each interface outputs the data to memory.
I want to be able to both transmit data from the interface cores, read data
from them and configure them (baud rate for example for UART). How can I do
this? Can I use the Wishbone bus and build a master core to drive the
operations, the interface cores being the slaves? Is it much easier if
don't use the Wishbone and just build my own interconnections bus?
Basically my question is how do large design connect cores, do they all use
a microprocessor? Looks like it by what I see on Xilinx' website, for
example.

Thanks

	   
					
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>Hi,
>
>I have a design in which I use multiple cores for connecting to different
>interfaces: SPI, I2C, UART, etc. Each interface outputs the data to
memory.
>I want to be able to both transmit data from the interface cores, read
data
>from them and configure them (baud rate for example for UART). How can I
do
>this? Can I use the Wishbone bus and build a master core to drive the
>operations, the interface cores being the slaves? Is it much easier if
>don't use the Wishbone and just build my own interconnections bus?
>Basically my question is how do large design connect cores, do they all
use
>a microprocessor? Looks like it by what I see on Xilinx' website, for
>example.
>
>Thanks

What you need is a bus to connect your modules to memory. Usually the
devices you mention would be slaves on the bus and you would have a
processor as a master to read the data and send it to memory. There are a
number of standard buses like PLB from IBM and AMBA from ARM. Xilinx have
used PLB in the past but are now using buses from ARM. I havent used
Wishbone but I dont see why you could not. You could design your own simple
bus using some mux and control signals. It all depends how complex you need
it.

Regards

Jon	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Thanks for the response. I know I can use Wishbone for interconnecting some
slave devices to a microprocessor but the idea is that I want to get away
without using a microprocessor. So the question is can another device,
other than microprocessor, be master on a Wishbone bus? Or on any other
bus... How can I get away without using a microprocessor? From your
experience designing a FSM is much more time consuming than using a simple
microprocessor core (in this case I have to spend time 1) learning to
program it and 2) writing the code)?

>>Hi,
>>
>>I have a design in which I use multiple cores for connecting to
different
>>interfaces: SPI, I2C, UART, etc. Each interface outputs the data to
>memory.
>>I want to be able to both transmit data from the interface cores, read
>data
>>from them and configure them (baud rate for example for UART). How can I
>do
>>this? Can I use the Wishbone bus and build a master core to drive the
>>operations, the interface cores being the slaves? Is it much easier if
>>don't use the Wishbone and just build my own interconnections bus?
>>Basically my question is how do large design connect cores, do they all
>use
>>a microprocessor? Looks like it by what I see on Xilinx' website, for
>>example.
>>
>>Thanks
>
>What you need is a bus to connect your modules to memory. Usually the
>devices you mention would be slaves on the bus and you would have a
>processor as a master to read the data and send it to memory. There are a
>number of standard buses like PLB from IBM and AMBA from ARM. Xilinx have
>used PLB in the past but are now using buses from ARM. I havent used
>Wishbone but I dont see why you could not. You could design your own
simple
>bus using some mux and control signals. It all depends how complex you
need
>it.
>
>Regards
>
>Jon	   
>					
>---------------------------------------		
>Posted through http://www.FPGARelated.com
>	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

On Dec 6, 4:00=A0pm, "sebas"
<tanarnelinistit@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.com> wrote:
> Thanks for the response. I know I can use Wishbone for interconnecting so=
me
> slave devices to a microprocessor but the idea is that I want to get away
> without using a microprocessor. So the question is can another device,
> other than microprocessor, be master on a Wishbone bus? Or on any other
> bus... How can I get away without using a microprocessor? From your
> experience designing a FSM is much more time consuming than using a simpl=
e
> microprocessor core (in this case I have to spend time 1) learning to
> program it and 2) writing the code)?

Of course you can do it any way you want.  How you configure the
peripherals depends on what the peripherals are expecting.  Are they
designed to be configured over wishbone?  Or are they designed to be
configured with direct connections?

It should be a simple matter to design a state machine to control your
data movements to and from each peripheral.  I have no idea how you
want this to work, so I can't make any specific suggestions.  I
suspect it could easily be done like a DMA controller.

Rick

On 12/6/2010 10:00 PM, sebas wrote:
> Thanks for the response. I know I can use Wishbone for
> interconnecting some slave devices to a microprocessor but the idea
> is that I want to get away without using a microprocessor. So the
> question is can another device, other than microprocessor, be master
> on a Wishbone bus? Or on any other bus... How can I get away without
> using a microprocessor? From your experience designing a FSM is much
> more time consuming than using a simple microprocessor core (in this
> case I have to spend time 1) learning to program it and 2) writing
> the code)?
>

Just to give you an example, I had to develop an fpga which was able to
control several heterogeneous devices (tdc with a jtag interface, adc,
charge amplifier, temperature sensor...). On top of it the fpga was a
slave on a custom serial link responsible for slow-control and real-time
data acquisition.
Everything was controlled through an FSM which handled error situations
and priority, but since I didn't have any idea of the existence of SoC
bus like the Wishbone, I spent half of the time designing the
interconnection bus.
In my case the data from each device was pretty well defined and with
very little programmable needs (except for the jtag), so an fsm did
the job pretty easily.
What I would recommend is to check what is the type of data you are
getting through your interfaces and then decide what kind of control you 
may need (a microprocessor/microcontroller or an fsm).

The Wishbone bus is pretty simple and you may find "wishbone compliant" 
cores for all the interfaces you mentioned on opencores.org.
Good luck,

Al

>>> Hi,
>>>
>>> I have a design in which I use multiple cores for connecting to
> different
>>> interfaces: SPI, I2C, UART, etc. Each interface outputs the data
>>> to
>> memory.
>>> I want to be able to both transmit data from the interface
>>> cores, read
>> data
>>> from them and configure them (baud rate for example for UART).
>>> How can I
>> do
>>> this? Can I use the Wishbone bus and build a master core to
>>> drive the operations, the interface cores being the slaves? Is it
>>> much easier if don't use the Wishbone and just build my own
>>> interconnections bus? Basically my question is how do large
>>> design connect cores, do they all
>> use
>>> a microprocessor? Looks like it by what I see on Xilinx'
>>> website, for example.
>>>
>>> Thanks
>>
>> What you need is a bus to connect your modules to memory. Usually
>> the devices you mention would be slaves on the bus and you would
>> have a processor as a master to read the data and send it to
>> memory. There are a number of standard buses like PLB from IBM and
>> AMBA from ARM. Xilinx have used PLB in the past but are now using
>> buses from ARM. I havent used Wishbone but I dont see why you could
>> not. You could design your own
> simple
>> bus using some mux and control signals. It all depends how complex
>> you
> need
>> it.
>>
>> Regards
>>
>> Jon  --------------------------------------- Posted through
>> http://www.FPGARelated.com
> --------------------------------------- Posted through
> http://www.FPGARelated.com

>Thanks for the response. I know I can use Wishbone for interconnecting
some
>slave devices to a microprocessor but the idea is that I want to get away
>without using a microprocessor. So the question is can another device,
>other than microprocessor, be master on a Wishbone bus? Or on any other
>bus... How can I get away without using a microprocessor? From your
>experience designing a FSM is much more time consuming than using a
simple
>microprocessor core (in this case I have to spend time 1) learning to
>program it and 2) writing the code)?
>

From personal experience, it is not terribly difficult to design an SPI or
I2C slave without local microprocessor or similar, that (on the other edge)
acts as a local bus master, writing or reading local bus memory-mapped
locations. Wishbone is a good-enough choice of bus for this.

You need to consider how you will handle access arbitration *when* 2 of
them want the bus at "the same time". Delaying writes until the bus is free
is quite easy. Handling the read access case may be a bit harder,
especially for SPI, although for I2C you just hold off the clock until the
data is ready.

Before you ask, I no longer have access to the code...
	   
					
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