Error in Clock Divider!

I have got a clock divider code as follows:

entity divClk8 is
   Port ( CLK : in std_logic;
          CLK_OUT : out std_logic);
end divClk8;

architecture Behavioral of divClk8 is
signal count : std_logic_vector (3 downto 0) := "1111";
signal reset : std_logic := '0';

begin
process(CLK)
begin
if(reset = '1') then
count <= "0000";
elsif(rising_edge(CLK)) then
count <= count + 1;
end if;
end process;
CLK_OUT <= count(3);
reset <= (count(3) and not(count(2))and not(count(1))and
not(count(0)));
end Behavioral;



But when I try to compile it using ModelSim I get the following error

--  No feasible entries for infix operator "+". Type error resolving
infix expression "+" as type ieee.std_logic_1164.std_logic_vector.



I didn't get what the error message says. A little word of advice
would be really helpful!

Regards
San

On Dec 29, 10:43=A0am, Santosh <santos...@gmail.com> wrote:
> I have got a clock divider code as follows:

> architecture Behavioral of divClk8 is
> signal count : std_logic_vector (3 downto 0) :=3D "1111";
> signal reset : std_logic :=3D '0';
>
> begin
> process(CLK)
> begin
> if(reset =3D '1') then
> count <=3D "0000";
> elsif(rising_edge(CLK)) then
> count <=3D count + 1;

>
> But when I try to compile it using ModelSim I get the following error
>
> -- =A0No feasible entries for infix operator "+". Type error resolving
> infix expression "+" as type ieee.std_logic_1164.std_logic_vector.
>

std_logic_vector signals do not have any math operators defined for
them.  A std_logic_vector is just a collection of bits with no numeric
interpretation.  To do what you want, you need to use a signal of type
unsigned which is defined in the package 'ieee.numeric_std'.  To fix
up the code:

- Add the line "use ieee.numeric_std.all" right after the line where
you currently have "library ieee"
- Change "signal count : std_logic_vector (3 downto 0)" to "signal
count : unsigned (3 downto 0)"

Kevin Jennings

Check your used libraries. Modelsim don't find an implementation
to add an integer 1 to a std_logic_vector.

On Wed, 2010-12-29 at 07:43 -0800, Santosh wrote:
> I have got a clock divider code as follows:
>=20
> entity divClk8 is
>    Port ( CLK : in std_logic;
>           CLK_OUT : out std_logic);
> end divClk8;
>=20
> architecture Behavioral of divClk8 is
> signal count : std_logic_vector (3 downto 0) :=3D "1111";
> signal reset : std_logic :=3D '0';
>=20
> begin
> process(CLK)
> begin
> if(reset =3D '1') then
> count <=3D "0000";
> elsif(rising_edge(CLK)) then
> count <=3D count + 1;
> end if;
> end process;
> CLK_OUT <=3D count(3);
> reset <=3D (count(3) and not(count(2))and not(count(1))and
> not(count(0)));
> end Behavioral;
>=20
>=20
>=20
> But when I try to compile it using ModelSim I get the following error
>=20
> --  No feasible entries for infix operator "+". Type error resolving
> infix expression "+" as type ieee.std_logic_1164.std_logic_vector.
>=20
>=20
>=20
> I didn't get what the error message says. A little word of advice
> would be really helpful!
>=20
> Regards
> San

On Dec 29, 8:43=A0am, Santosh <santos...@gmail.com> wrote:
> I have got a clock divider code as follows:
>
> entity divClk8 is
> =A0 =A0Port ( CLK : in std_logic;
> =A0 =A0 =A0 =A0 =A0 CLK_OUT : out std_logic);
> end divClk8;
>
> architecture Behavioral of divClk8 is
> signal count : std_logic_vector (3 downto 0) :=3D "1111";
> signal reset : std_logic :=3D '0';
>
> begin
> process(CLK)
> begin
> if(reset =3D '1') then
> count <=3D "0000";
> elsif(rising_edge(CLK)) then
> count <=3D count + 1;
> end if;
> end process;
> CLK_OUT <=3D count(3);
> reset <=3D (count(3) and not(count(2))and not(count(1))and
> not(count(0)));
> end Behavioral;
>
> But when I try to compile it using ModelSim I get the following error
>
> -- =A0No feasible entries for infix operator "+". Type error resolving
> infix expression "+" as type ieee.std_logic_1164.std_logic_vector.
>
> I didn't get what the error message says. A little word of advice
> would be really helpful!
>
> Regards
> San

In addition to the responses you've had so far, don't you need to
include the port for the reset line input and also include it in your
process sensitivity list?

Le 29/12/2010 16:43, Santosh a �crit :
> I have got a clock divider code as follows:
>
> entity divClk8 is
>     Port ( CLK : in std_logic;
>            CLK_OUT : out std_logic);
> end divClk8;
>
> architecture Behavioral of divClk8 is
> signal count : std_logic_vector (3 downto 0) := "1111";
> signal reset : std_logic := '0';
>
> begin
> process(CLK)
> begin
> if(reset = '1') then
> count<= "0000";
> elsif(rising_edge(CLK)) then
> count<= count + 1;
> end if;
> end process;
> CLK_OUT<= count(3);
> reset<= (count(3) and not(count(2))and not(count(1))and
> not(count(0)));
> end Behavioral;
>
>
>
> But when I try to compile it using ModelSim I get the following error
>
> --  No feasible entries for infix operator "+". Type error resolving
> infix expression "+" as type ieee.std_logic_1164.std_logic_vector.

What do you plan to do with your divided clock output ? It will be a 
short glith-like pulse that will be very dependent on many things 
(mainly temperature) that won't be very usable.

Nicolas

Overloading will allow you to add integers like 1 (such as for basic
counters) to your std_logic_vector's. One of the IEEE libraries will
allow you to do this if you include the right one. Don't remember
which one off top of my head.

Some other observations:
- You are missing a reset input.
- You don't need to include reset into sensitivity list if you are
treating it synchronously.
- If you maintain std_logic_vector(3 downto 0) type OR use integer of
"range 0 to 3" there is no need to reset counter if you intend to
rollover at max (all 1's) value.

John

On 29 Dez. 2010, 17:32, Dave <starfire...@cableone.net> wrote:

> In addition to the responses you've had so far, don't you need to
> include the port for the reset line input and also include it in your
> process sensitivity list?

No as this seems to be a synchronous reset which is internal
generated.

On 29 Dez. 2010, 19:22, Nicolas Matringe <nicolas.matri...@fre.fre>
wrote:
> Le 29/12/2010 16:43, Santosh a crit :
>
>
>
> > I have got a clock divider code as follows:
>
> > entity divClk8 is
> > =A0 =A0 Port ( CLK : in std_logic;
> > =A0 =A0 =A0 =A0 =A0 =A0CLK_OUT : out std_logic);
> > end divClk8;
>
> > architecture Behavioral of divClk8 is
> > signal count : std_logic_vector (3 downto 0) :=3D "1111";
> > signal reset : std_logic :=3D '0';
>
> > begin
> > process(CLK)
> > begin
> > if(reset =3D '1') then
> > count<=3D "0000";
> > elsif(rising_edge(CLK)) then
> > count<=3D count + 1;
> > end if;
> > end process;
> > CLK_OUT<=3D count(3);
> > reset<=3D (count(3) and not(count(2))and not(count(1))and
> > not(count(0)));
> > end Behavioral;
>
> > But when I try to compile it using ModelSim I get the following error
>
> > -- =A0No feasible entries for infix operator "+". Type error resolving
> > infix expression "+" as type ieee.std_logic_1164.std_logic_vector.
>
> What do you plan to do with your divided clock output ? It will be a
> short glith-like pulse that will be very dependent on many things
> (mainly temperature) that won't be very usable.

Please explain your problems with the functional code?
I would have written it a bit shorter, but can't see a problem in
generating a divided clock with 8 cycles '0' and 8 cycles '1'

bye Thomas

"Santosh" <santos2k7@gmail.com> wrote in message 
news:17ff8d8d-0fa9-41d3-8946-53879f254399@r8g2000prm.googlegroups.com...
>I have got a clock divider code as follows:
>
> entity divClk8 is
>   Port ( CLK : in std_logic;
>          CLK_OUT : out std_logic);
> end divClk8;
>
> architecture Behavioral of divClk8 is
> signal count : std_logic_vector (3 downto 0) := "1111";
> signal reset : std_logic := '0';
>
> begin
> process(CLK)
> begin
> if(reset = '1') then
> count <= "0000";
> elsif(rising_edge(CLK)) then
> count <= count + 1;
> end if;
> end process;
> CLK_OUT <= count(3);
> reset <= (count(3) and not(count(2))and not(count(1))and
> not(count(0)));
> end Behavioral;
>
>
>
> But when I try to compile it using ModelSim I get the following error
>
> --  No feasible entries for infix operator "+". Type error resolving
> infix expression "+" as type ieee.std_logic_1164.std_logic_vector.

Lots of potential issues with this code, but try:
count <= count + "1"; -- now with quotes on the 1

On Jan 3, 9:08=A0am, Thomas Stanka <usenet_nospam_va...@stanka-web.de>
wrote:
> On 29 Dez. 2010, 17:32, Dave <starfire...@cableone.net> wrote:
>
> > In addition to the responses you've had so far, don't you need to
> > include the port for the reset line input and also include it in your
> > process sensitivity list?
>
> No as this seems to be a synchronous reset which is internal
> generated.

You might want to take another look.  The OP coded an asynchronous
reset but forgot to include the reset signal in the sensitivity list.

KJ