Verilog Book for VHDL Users

On Jan 21, 10:04=A0am, Anssi Saari <a...@sci.fi> wrote:
> rickman <gnu...@gmail.com> writes:
> > I'm curious, why are you using VHDL more now? =A0Is this a job
> > requirement or do you prefer VHDL? =A0
>
> Job requirement. Euroland is VHDLland too, with some exceptions.
> Usually means customer is somewhere else, like in North America or
> Asia. Even then, Verilog may be the result of autoconversion from
> VHDL...
>
> > Was there something about Verilog you didn't like?
>
> I liked it just fine for design. Didn't much care for writing
> testbenches in it. Most of my Verilog work was for telecom. For
> example, generating ATM cells and sending them to the design was just
> awful. Should've done it in Perl and put the data in a file. In fact,
> I did that for the received data.
>
> I'm not too keen on VHDL, but it gets the job done. I used to hate the
> strong typing and required conversions, but I guess I don't mind that
> much any more. Maybe it's influence from my recent interest in Python
> too.

That was the one place where I used Verilog in the past, at a telecom
test equipment company.  I'm near Washington, DC and a lot of the jobs
around here are government.  I was in a government contractor job when
I learned HDL, so it was VHDL.  Now I want to learn Verilog as well as
I know VHDL and it is ticking me off a bit that I'm being told there
are NO good text books in it.

I've heard that Europe is very VHDL oriented.  I have no idea what
predominates in the far East.  I'm curious about that.

Rick

Anssi Saari <as@sci.fi> writes:

>> Was there something about Verilog you didn't like?
>
> I liked it just fine for design. Didn't much care for writing
> testbenches in it. Most of my Verilog work was for telecom. For

I'm the opposite :-) VHDL is ok for design, but not for testbenches.
SystemVerilog provides a much higher level of abstraction and features
like assertions, covergroups, and randomize classes for making
constraint random based testbenches.

//Petter

On Jan 16, 4:36 pm, Mike Treseler <mtrese...@gmail.com> wrote:
> On 1/15/2011 12:09 PM, rickman wrote:
>
> > This is starting to sound like VHDL...!  I don't mind being explicit.
> > It is just that in VHDL it can get rather confusing as to what you
> > need to be explicit about or how exactly to be explicit.
>
> > I find it hard to believe that there are no good texts on this.
>
> It is true.
> I found this one slightly useful:http://www.google.com/search?q=botros+isbn+1584508558
>
> It's the only book of side by side vhdl|verilog examples in print.
> But that is all it is -- simple synthesis examples and a short
> explanation. No language reference or simulation examples.
> But it's a quick way for a vhdl guy to get started
> on verilog synthesis, and the price is right.
>
>         -- Mike Treseler

Why do you say this is the "only" text?  I know of at least two others
that cover both VHDL and Verilog.  One is Ben Cohen's book, "Real Chip
Design and Verification Using Verilog and VHDL".  The other I have,
Douglas J. Smith, "HDL Chip Design".  The Smith book has side by side
examples of both like you describe for the Botros book, but I can't
say about the Cohen book since I haven't seen it.

I will say this is the only affordable one of the three.  The other
two are $167 and $135!  Thats just too rich for my blood.

Rick