Wow! No TestbenchWow!

>One question though: if the task sendChar is called concurrently from
>different procedural blocks in a way that the calls are overlapping, I
>think the result would be a great mess (I am saying this as a not so
great
>lover of how Verilog works).
>
>Is there a simple way to deal with collisions like that? Or will the
>simplicity be lost then for the most part?

That's the reason why we have to use protected types to access
methods/functions directly from a package or another entity. :)
Peter Ashenden's book explains well...

regards, daniel

	   
					
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On Friday, May 4, 2012 3:39:27 AM UTC+8, daniel.kho wrote:

> /* The testbench. */
> library ieee; use ieee.std_logic_1164.all;
> entity justTryThisOne is end entity justTryThisOne;
> 
> architecture noTestbenchInst of justTryThisOne is
>     signal serial_TxD: std_ulogic;
>     alias txGenerator is <<variable @work.uartPkg.uartTx:
> @work.uartPkg.simulatedUartTransmitter>>;
> begin
>     tester: process is begin
>         txGenerator.setBitTime(104000);
>         wait for 1 us;
>         txGenerator.sendChar('h');
>         txGenerator.sendChar('i');
>         txGenerator.sendChar('!');
>         wait for 1 us;
>     end process tester;
> end architecture noTestbenchInst;

Sorry, I guess serial_TxD should have been:
    alias serial_TxD is <<signal @work.uartPkg.TxD: std_ulogic>>;
instead of declared as another signal within the architecture.

This way, you can check/monitor the output of the UART from this same testbench.

-daniel