Nanosecond pulse generator using Spartan-3E

Hello, I'm a novice in FPGA, so please forgive me if I'm asking simple
questions.

I've got Spartan-3E Evaluation Kit and I need to realize a programmable
generator of pulses of nanosecond duration. The problem is as follows: I've
got a trigger pulse and I need to generate a TTL pulse of nanosecond
duration with programmable width (with step about 200-500 ps, range 2 ns -
100 ns (for example)) and programmable delay (with 200-500 ps step). The
maximum delay from in to out must not be more than 10 ns.
Actually I need to realize a wide-range pulse generator, but as I
understand there is no problem generate wide pulses (more than 100 ns) with
larger step (10 ns) working in synchroneous regime and using clock. But for
narrow pulses I think I should work in asynchroneous regime. I could use
elements with known delay and link them into a chain.
If it possible to realize such project using Spartan-3E FPGA chip, or maybe
I need something from Virtex family.

Thank you in advance.
Alex.



	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Un bel giorno Alex digit�:

> I've got Spartan-3E Evaluation Kit and I need to realize a programmable
> generator of pulses of nanosecond duration. The problem is as follows: I've
> got a trigger pulse and I need to generate a TTL pulse of nanosecond
> duration with programmable width (with step about 200-500 ps, range 2 ns -
> 100 ns (for example)) and programmable delay (with 200-500 ps step). The
> maximum delay from in to out must not be more than 10 ns.
> Actually I need to realize a wide-range pulse generator, but as I
> understand there is no problem generate wide pulses (more than 100 ns) with
> larger step (10 ns) working in synchroneous regime and using clock. But for
> narrow pulses I think I should work in asynchroneous regime. I could use
> elements with known delay and link them into a chain.

You could try to feed a DCM with a clock, generate another clock with a
very small phase difference with the first one (you have resolutions down
to tens of ps) and then try to XOR them with some combinatorial logic (or
by using an output buffer with enable).

-- 
emboliaschizoide.splinder.com

Alex <aivochkin@n_o_s_p_a_m.gmail.com> wrote:
 
> I've got Spartan-3E Evaluation Kit and I need to realize a programmable
> generator of pulses of nanosecond duration. The problem is as follows: I've
> got a trigger pulse and I need to generate a TTL pulse of nanosecond
> duration with programmable width (with step about 200-500 ps, range 2 ns -
> 100 ns (for example)) and programmable delay (with 200-500 ps step). The
> maximum delay from in to out must not be more than 10 ns.

Can you give some hint as to why you need pulses like that?  
That might have some influence on the type of design that can 
generate them.  Also, if it is a homework problem, you will get
appropriate answers for that case.

> Actually I need to realize a wide-range pulse generator, but as I
> understand there is no problem generate wide pulses (more than 100 ns) with
> larger step (10 ns) working in synchroneous regime and using clock. But for
> narrow pulses I think I should work in asynchroneous regime. I could use
> elements with known delay and link them into a chain.

There are some designs like that.  It isn't easy, but sometimes
it is possible.  There are also some mixed analog/digital solutions
to problems like this.  You can, for example, charge a capacitor
with a current determined by the FPGA, and, through a comparitor
on the output, generate the pulse.

> If it possible to realize such project using Spartan-3E FPGA chip, 
> or maybe I need something from Virtex family.

I believe that Virtex is often faster, and so may allow for clock
rates fast enough to do this as synchronous logic.

-- glen

On Monday, February 28, 2011 9:36:44 AM UTC-5, Alex wrote:
> Hello, I'm a novice in FPGA, so please forgive me if I'm asking simple
> questions.
> 
> I've got Spartan-3E Evaluation Kit and I need to realize a programmable
> generator of pulses of nanosecond duration. The problem is as follows: I've
> got a trigger pulse and I need to generate a TTL pulse of nanosecond
> duration with programmable width (with step about 200-500 ps, range 2 ns -
> 100 ns (for example)) and programmable delay (with 200-500 ps step). The
> maximum delay from in to out must not be more than 10 ns.
> Actually I need to realize a wide-range pulse generator, but as I
> understand there is no problem generate wide pulses (more than 100 ns) with
> larger step (10 ns) working in synchroneous regime and using clock. But for
> narrow pulses I think I should work in asynchroneous regime. I could use
> elements with known delay and link them into a chain.
> If it possible to realize such project using Spartan-3E FPGA chip, or maybe
> I need something from Virtex family.
> 
> Thank you in advance.
> Alex.
> 
> 
> 
> 	   
> 					
> ---------------------------------------		
> Posted through http://www.FPGARelated.com

What you're trying to do will be very difficult in any
FPGA unless the input is periodic (like a clock).  Any
kind of asynchronous delay derived from internal prop
delays (delay through LUT's) will have very wide
variations over process, temperature and voltage.
Spartan 3E does not contain output delay elements
in the IOB's.  Virtex 4 or Virtex 5 have calibrated
output delay elements, but again you'll have issues
with the small total delay through the chip.

If your input signal is periodic and running at a
frequency that can lock a DCM, then you have more
options.  For example running the input to more
than one DCM, and using programmable phase shifting.
You could also possible use a DDR output flop
with a clock tied to each DCM, however you'd
still have problems when the two clock phases
become very close to eachother.

-- Gabor

On Feb 28, 12:15=A0pm, glen herrmannsfeldt <g...@ugcs.caltech.edu>
wrote:
>
> I believe that Virtex is often faster, and so may allow for clock
> rates fast enough to do this as synchronous logic.
>
> -- glen

Unless my math is wrong, 200pS increments require a 5GHz clock.

Perhaps the Virtex-12 will be that fast, but the -7 isn't.

There may be a way to do what the OP wants with IODELAY elements, but
would involve real research.

RK

On Monday, February 28, 2011 5:32:40 PM UTC-5, NeedCleverHandle wrote:
> 
> Unless my math is wrong, 200pS increments require a 5GHz clock.
> 
> Perhaps the Virtex-12 will be that fast, but the -7 isn't.
> 
> There may be a way to do what the OP wants with IODELAY elements, but
> would involve real research.
> 
> RK



I think he was looking for a delay-based solution,
but the problem is that Spartan 3E does not have
IODELAY, only IDELAY, and those are not as flexible
as even the IDELAY of Spartan 3A.  Also to get a
calibrated delay element you need to go to a
V4 or V5 part.

-- Gabor

Alex wrote:
> Hello, I'm a novice in FPGA, so please forgive me if I'm asking simple
> questions.
> 
> I've got Spartan-3E Evaluation Kit and I need to realize a programmable
> generator of pulses of nanosecond duration. The problem is as follows: I've
> got a trigger pulse and I need to generate a TTL pulse of nanosecond
> duration with programmable width (with step about 200-500 ps, range 2 ns -
> 100 ns (for example)) and programmable delay (with 200-500 ps step). The
> maximum delay from in to out must not be more than 10 ns.
> Actually I need to realize a wide-range pulse generator, but as I
> understand there is no problem generate wide pulses (more than 100 ns) with
> larger step (10 ns) working in synchroneous regime and using clock. But for
> narrow pulses I think I should work in asynchroneous regime. I could use
> elements with known delay and link them into a chain.
> If it possible to realize such project using Spartan-3E FPGA chip, or maybe
> I need something from Virtex family.
> 
> Thank you in advance.
> Alex.
> 
> 
> 
> 	   
> 					
> ---------------------------------------		
> Posted through http://www.FPGARelated.com


Ask John Larkin over in sci.electronics.design.


Basically, sub-ns resolution delays with large (up to seconds) total
delays are done with mixed signal verniers coupled to digital counter
arrangements.

The counter stuff is easy.  I have yet to fully grasp how the vernier
stuff works, while also having fully asynchronous trigger-ability.


-- 
_____________________
Mr.CRC
crobcBOGUS@REMOVETHISsbcglobal.net
SuSE 10.3 Linux 2.6.22.17

Mr.CRC <crobcBOGUS@removethissbcglobal.net> wrote:

(snip)
>> I've got Spartan-3E Evaluation Kit and I need to realize a programmable
>> generator of pulses of nanosecond duration. The problem is as follows: I've
>> got a trigger pulse and I need to generate a TTL pulse of nanosecond
>> duration with programmable width (with step about 200-500 ps, range 2 ns -
>> 100 ns (for example)) and programmable delay (with 200-500 ps step). The
>> maximum delay from in to out must not be more than 10 ns.
(snip)

> Ask John Larkin over in sci.electronics.design.
 
> Basically, sub-ns resolution delays with large (up to seconds) total
> delays are done with mixed signal verniers coupled to digital counter
> arrangements.

I used to know about a TDC, (see wikipedia Time_to_digital_converter )
which works by charging a capacitor for the appropriate amount of
time, and then measuring the voltage with an ADC.  That is used for
the fine timing (low eight bits), and a counter for the course timing.

I am not sure how the analog part is calibrated, but it seems to
me that it could be done with a PLL.  

I believe that a similar system could be used in reverse.
In an FPGA, there is the complication of knowing the different
delays, which are needed for calibration.  

The wikipedia page mentions a Vernier Johnson counter, which would
seem to be more digital.  
 
> The counter stuff is easy.  I have yet to fully grasp how the vernier
> stuff works, while also having fully asynchronous trigger-ability.

If you can generate two delays off the trigger at the appropriate
resolution, then the pulse can be the difference between the two.
Again, calibration is the hard part.

-- glen

Am 11.03.2011 04:24, schrieb glen herrmannsfeldt:
> I used to know about a TDC, (see wikipedia Time_to_digital_converter )

The wikipedia article about TDC is a total mess.  I wouldn't recommend
it to anyone.

Thomas

maybe just open enough door(s) to have the correct delay without
thinking more and the homework is done ?