On Mar 28, 2:25=A0am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:> On Mar 27, 9:57=A0am, Pratap <pratap.i...@gmail.com> wrote: > > > > > On Mar 27, 9:39=A0pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > > > On Mar 26, 8:41=A0pm, Pratap <pratap.i...@gmail.com> wrote: > > > > > On Mar 27, 6:39=A0am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrot=e:> > > > > > On Mar 26, 7:53=A0am, Pratap <pratap.i...@gmail.com> wrote: > > > > > > > > The MGT TXP/TXN/RXP/RXN pins are dedicated pins that can only=be used> > > > > > > by the MGTs. =A0In the Virtex-II Pro FPGA family the MGT refe=rence clock> > > > > > > pins were normal I/Os that had extra dedicated routing to the=MGTs.> > > > > > > > Are you using a Xilinx board? =A0If so which one is it? > > > > > > > > What are the IO location constraints that you are using for t=he output> > > > > > > and input paths? > > > > > > > > Ed McGettigan > > > > > > > -- > > > > > > > Xilinx Inc. > > > > > > > Hello, > > > > > > I am using the Virtex II Pro development board for my project. > > > > > > I am pasting all the IO constraints written to the ucf file. > > > > > > The signals to take out and then feed in are "inp_for_TI_chip" =and> > > > > > "op_from_TI_chip" respectively. > > > > > > > NET "reset_in" LOC =3D "AH1" | IOSTANDARD =3D LVCMOS25; > > > > > > #LEFT P/B > > > > > > > NET "clk_in" LOC =3D "G15" | IOSTANDARD =3D LVCMOS25; > > > > > > #EXTERNAL_CLOCK_P > > > > > > > NET "samp_clk" LOC =3D "F15" | IOSTANDARD =3D LVCMOS25; > > > > > > #EXTERNAL_CLOCK_N > > > > > > > NET "op_from_TI_chip" =A0LOC =3D "A6" | IOSTANDARD =3D LVCMOS25=;> > > > > > #MGT_TXP > > > > > > > NET "inp_for_TI_chip" =A0LOC =3D "A7" | IOSTANDARD =3D LVCMOS25=| SLEW =3D> > > > > > FAST | DRIVE =3D 8 ; > > > > > > #MGT_TXN > > > > > > > NET "ti_delay_chip_cntl" =A0LOC =3D "R9" | IOSTANDARD =3D LVCMO=S25 | SLEW =3D> > > > > > FAST | DRIVE =3D 8 ; > > > > > > #J5-11 > > > > > > > NET "dir_fine_delay" =A0LOC =3D "P1" | IOSTANDARD =3D LVCMOS25 =| SLEW =3D FAST> > > > > > | DRIVE =3D 8 ; > > > > > > #J5-15 > > > > > > > NET "board_in1" =A0LOC =3D "AB1" | IOSTANDARD =3D LVCMOS25 | SL=EW =3D FAST |> > > > > > DRIVE =3D 8 ; > > > > > > #J6-27 > > > > > > > NET "board_in2" =A0LOC =3D "W8" | IOSTANDARD =3D LVCMOS25 | SLE=W =3D FAST |> > > > > > DRIVE =3D 8 ; > > > > > > #J6-35 > > > > > > > NET "cleaned_clk1" =A0LOC =3D "R3" | IOSTANDARD =3D LVCMOS25 | =SLEW =3D FAST |> > > > > > DRIVE =3D 8 ; > > > > > > #J5-31 > > > > > > > NET "cleaned_clk2" =A0LOC =3D "U3" | IOSTANDARD =3D LVCMOS25 | =SLEW =3D FAST |> > > > > > DRIVE =3D 8 ; > > > > > > #J5-39 > > > > > > > NET "status(3)" LOC =3D "AC4" | IOSTANDARD =3D LVCMOS25 | SLEW ==3D SLOW |> > > > > > DRIVE =3D 12 ; > > > > > > NET "status(2)" LOC =3D "AC3" | IOSTANDARD =3D LVCMOS25 | SLEW ==3D SLOW |> > > > > > DRIVE =3D 12 ; > > > > > > NET "status(1)" LOC =3D "AA6" | IOSTANDARD =3D LVCMOS25 | SLEW ==3D SLOW |> > > > > > DRIVE =3D 12 ; > > > > > > NET "status(0)" LOC =3D "AA5" | IOSTANDARD =3D LVCMOS25 | SLEW ==3D SLOW |> > > > > > DRIVE =3D 12 ; > > > > > > > Thanks, > > > > > > Pratap > > > > > > The UCF file constraints have regular IO location assignments to =A7> > > > > and A6 which are the MGT TXP/TXN pins. =A0These locations are not=valid> > > > > for anything other than MGT TXP/TXN pins and your original post > > > > > indicated that you had changed these to other locations and it wo=rked.> > > > > > I'm confused. =A0What exactly is your question or problem? > > > > > > Ed McGettigan > > > > > -- > > > > > Xilinx Inc. > > > > > Yes, > > > > This is the ucf file that is not working. The ucf file that ensures > > > > that there is toggling at all the signal ports is as follows. > > > > > NET "op_from_TI_chip" =A0LOC =3D "F16" | IOSTANDARD =3D LVCMOS25; > > > > #MGT_CLK_P > > > > > NET "inp_for_TI_chip" =A0LOC =3D "G16" | IOSTANDARD =3D LVCMOS25 | =SLEW =3D> > > > FAST | DRIVE =3D 8 ; > > > > #MGT_CLK_N > > > > > My exact problem is in understanding why in the case when I connect > > > > the pins intended to be interfaced with the other chip to F16 and > > > > G16(The externally non-accessible ports on board) , I get the signa=ls> > > > at the output port. If I connect those two signals to any other =A0=pin,> > > > it doesn't seem to work. > > > > I hope the problem is clear now. > > > > > Thanks, > > > > Pratap- Hide quoted text - > > > > > - Show quoted text - > > > > Sorry, it still isn't very clear and you still haven't identified > > > which exact board you are using (vendor and model). > > > > As I said twice already, the MGT TXP/TXN pins A6/A7 cannot be used fo=r> > > anything other that the MGT. =A0For this device pins F16 and G16 are > > > regular IO and also MGT reference clock input pins so they can be use=d> > > for inputs or outputs. > > > > > If I connect those two signals to any other =A0pin, > > > > it doesn't seem to work. > > > > It isn't clear what you mean by any other pin and what doesn't work. > > > > Ed McGettigan > > > -- > > > Xilinx Inc. > > > OK. > > Let me rephrase the problem. > > All I want is, I want to take a signal out of the Xilinx Virtex II Pro > > board which is fed to the FPGA pin "G15" (EXT_CLK_N). > > If I give a signal to "G15" (EXT_CLK_N) and take it out of FPGA > > through the pin "F15" (EXT_CLK_P), it works absolutely fine. > > But when I use both the pins F15 and G15 for two different input > > signals, and want to take a delayed version of the signal fed to > > "G15", by routing it through any of the pins in the connector series > > located on J5 or J6 or J37(Eg AC6 on J37-A14), it doesn't come out. I > > want to stimulate another chip with this delayed signal coming from > > FPGA. The P&R completes without any problem when I use the Pin J37-A14 > > or any other pin, but when I am checking the signal at that pin by > > connecting an oscilloscope probe there, I don't see any signal there. > > This is what I mean by, things don't work. Is is there any issue in > > taking out the signals connected to F15 or G15 once I use both of > > those pins as inputs? If yes, why so and what is the way around? > > I hope the question is more straight forward now and thanks for the > > patience shown in understanding the issue. > > Thanks, > > Pratap- Hide quoted text - > > > - Show quoted text - > > Pratap, > > You still haven't said what board you are using. who made the board > and what is the model name? =A0This is very important information. > > Ed McGettigan > -- > Xilinx Inc.Sorry, Actually, it never struck to my mind that there are other varieties of Xilinx Virtex-II Pro. Here is the Target Device name: "Virtex-II Pro XC2VP30-7ff896" Product link: http://www.xilinx.com/products/devkits/XUPV2P.htm Image: http://www.xilinx.com/products/devkits/XUPV2P-image.htm Thanks, Pratap
How to take signals fed to EXT_CLK_P and EXT_CLK_N SMA connectors from a Virtex II Pro board
Started by ●March 25, 2011
Reply by ●March 27, 20112011-03-27
Reply by ●March 27, 20112011-03-27
On Mar 27, 3:23=A0pm, Pratap <pratap.i...@gmail.com> wrote:> On Mar 28, 2:25=A0am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > > > > > > On Mar 27, 9:57=A0am, Pratap <pratap.i...@gmail.com> wrote: > > > > On Mar 27, 9:39=A0pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > > > > On Mar 26, 8:41=A0pm, Pratap <pratap.i...@gmail.com> wrote: > > > > > > On Mar 27, 6:39=A0am, Ed McGettigan <ed.mcgetti...@xilinx.com> wr=ote:> > > > > > > On Mar 26, 7:53=A0am, Pratap <pratap.i...@gmail.com> wrote: > > > > > > > > > The MGT TXP/TXN/RXP/RXN pins are dedicated pins that can on=ly be used> > > > > > > > by the MGTs. =A0In the Virtex-II Pro FPGA family the MGT re=ference clock> > > > > > > > pins were normal I/Os that had extra dedicated routing to t=he MGTs.> > > > > > > > > Are you using a Xilinx board? =A0If so which one is it? > > > > > > > > > What are the IO location constraints that you are using for=the output> > > > > > > > and input paths? > > > > > > > > > Ed McGettigan > > > > > > > > -- > > > > > > > > Xilinx Inc. > > > > > > > > Hello, > > > > > > > I am using the Virtex II Pro development board for my project=.> > > > > > > I am pasting all the IO constraints written to the ucf file. > > > > > > > The signals to take out and then feed in are "inp_for_TI_chip=" and> > > > > > > "op_from_TI_chip" respectively. > > > > > > > > NET "reset_in" LOC =3D "AH1" | IOSTANDARD =3D LVCMOS25; > > > > > > > #LEFT P/B > > > > > > > > NET "clk_in" LOC =3D "G15" | IOSTANDARD =3D LVCMOS25; > > > > > > > #EXTERNAL_CLOCK_P > > > > > > > > NET "samp_clk" LOC =3D "F15" | IOSTANDARD =3D LVCMOS25; > > > > > > > #EXTERNAL_CLOCK_N > > > > > > > > NET "op_from_TI_chip" =A0LOC =3D "A6" | IOSTANDARD =3D LVCMOS=25;> > > > > > > #MGT_TXP > > > > > > > > NET "inp_for_TI_chip" =A0LOC =3D "A7" | IOSTANDARD =3D LVCMOS=25 | SLEW =3D> > > > > > > FAST | DRIVE =3D 8 ; > > > > > > > #MGT_TXN > > > > > > > > NET "ti_delay_chip_cntl" =A0LOC =3D "R9" | IOSTANDARD =3D LVC=MOS25 | SLEW =3D> > > > > > > FAST | DRIVE =3D 8 ; > > > > > > > #J5-11 > > > > > > > > NET "dir_fine_delay" =A0LOC =3D "P1" | IOSTANDARD =3D LVCMOS2=5 | SLEW =3D FAST> > > > > > > | DRIVE =3D 8 ; > > > > > > > #J5-15 > > > > > > > > NET "board_in1" =A0LOC =3D "AB1" | IOSTANDARD =3D LVCMOS25 | =SLEW =3D FAST |> > > > > > > DRIVE =3D 8 ; > > > > > > > #J6-27 > > > > > > > > NET "board_in2" =A0LOC =3D "W8" | IOSTANDARD =3D LVCMOS25 | S=LEW =3D FAST |> > > > > > > DRIVE =3D 8 ; > > > > > > > #J6-35 > > > > > > > > NET "cleaned_clk1" =A0LOC =3D "R3" | IOSTANDARD =3D LVCMOS25 =| SLEW =3D FAST |> > > > > > > DRIVE =3D 8 ; > > > > > > > #J5-31 > > > > > > > > NET "cleaned_clk2" =A0LOC =3D "U3" | IOSTANDARD =3D LVCMOS25 =| SLEW =3D FAST |> > > > > > > DRIVE =3D 8 ; > > > > > > > #J5-39 > > > > > > > > NET "status(3)" LOC =3D "AC4" | IOSTANDARD =3D LVCMOS25 | SLE=W =3D SLOW |> > > > > > > DRIVE =3D 12 ; > > > > > > > NET "status(2)" LOC =3D "AC3" | IOSTANDARD =3D LVCMOS25 | SLE=W =3D SLOW |> > > > > > > DRIVE =3D 12 ; > > > > > > > NET "status(1)" LOC =3D "AA6" | IOSTANDARD =3D LVCMOS25 | SLE=W =3D SLOW |> > > > > > > DRIVE =3D 12 ; > > > > > > > NET "status(0)" LOC =3D "AA5" | IOSTANDARD =3D LVCMOS25 | SLE=W =3D SLOW |> > > > > > > DRIVE =3D 12 ; > > > > > > > > Thanks, > > > > > > > Pratap > > > > > > > The UCF file constraints have regular IO location assignments t=o A7> > > > > > and A6 which are the MGT TXP/TXN pins. =A0These locations are n=ot valid> > > > > > for anything other than MGT TXP/TXN pins and your original post > > > > > > indicated that you had changed these to other locations and it =worked.> > > > > > > I'm confused. =A0What exactly is your question or problem? > > > > > > > Ed McGettigan > > > > > > -- > > > > > > Xilinx Inc. > > > > > > Yes, > > > > > This is the ucf file that is not working. The ucf file that ensur=es> > > > > that there is toggling at all the signal ports is as follows. > > > > > > NET "op_from_TI_chip" =A0LOC =3D "F16" | IOSTANDARD =3D LVCMOS25; > > > > > #MGT_CLK_P > > > > > > NET "inp_for_TI_chip" =A0LOC =3D "G16" | IOSTANDARD =3D LVCMOS25 =| SLEW =3D> > > > > FAST | DRIVE =3D 8 ; > > > > > #MGT_CLK_N > > > > > > My exact problem is in understanding why in the case when I conne=ct> > > > > the pins intended to be interfaced with the other chip to F16 and > > > > > G16(The externally non-accessible ports on board) , I get the sig=nals> > > > > at the output port. If I connect those two signals to any other ==A0pin,> > > > > it doesn't seem to work. > > > > > I hope the problem is clear now. > > > > > > Thanks, > > > > > Pratap- Hide quoted text - > > > > > > - Show quoted text - > > > > > Sorry, it still isn't very clear and you still haven't identified > > > > which exact board you are using (vendor and model). > > > > > As I said twice already, the MGT TXP/TXN pins A6/A7 cannot be used =for> > > > anything other that the MGT. =A0For this device pins F16 and G16 ar=e> > > > regular IO and also MGT reference clock input pins so they can be u=sed> > > > for inputs or outputs. > > > > > > If I connect those two signals to any other =A0pin, > > > > > it doesn't seem to work. > > > > > It isn't clear what you mean by any other pin and what doesn't work=.> > > > > Ed McGettigan > > > > -- > > > > Xilinx Inc. > > > > OK. > > > Let me rephrase the problem. > > > All I want is, I want to take a signal out of the Xilinx Virtex II Pr=o> > > board which is fed to the FPGA pin "G15" (EXT_CLK_N). > > > If I give a signal to "G15" (EXT_CLK_N) and take it out of FPGA > > > through the pin "F15" (EXT_CLK_P), it works absolutely fine. > > > But when I use both the pins F15 and G15 for two different input > > > signals, and want to take a delayed version of the signal fed to > > > "G15", by routing it through any of the pins in the connector series > > > located on J5 or J6 or J37(Eg AC6 on J37-A14), it doesn't come out. I > > > want to stimulate another chip with this delayed signal coming from > > > FPGA. The P&R completes without any problem when I use the Pin J37-A1=4> > > or any other pin, but when I am checking the signal at that pin by > > > connecting an oscilloscope probe there, I don't see any signal there. > > > This is what I mean by, things don't work. Is is there any issue in > > > taking out the signals connected to F15 or G15 once I use both of > > > those pins as inputs? If yes, why so and what is the way around? > > > I hope the question is more straight forward now and thanks for the > > > patience shown in understanding the issue. > > > Thanks, > > > Pratap- Hide quoted text - > > > > - Show quoted text - > > > Pratap, > > > You still haven't said what board you are using. who made the board > > and what is the model name? =A0This is very important information. > > > Ed McGettigan > > -- > > Xilinx Inc. > > Sorry, > Actually, it never struck to my mind that there are other varieties of > Xilinx Virtex-II Pro. > Here is the Target Device name: "Virtex-II Pro XC2VP30-7ff896" > Product link:http://www.xilinx.com/products/devkits/XUPV2P.htm > Image:http://www.xilinx.com/products/devkits/XUPV2P-image.htm > Thanks, > Pratap- Hide quoted text - > > - Show quoted text -Virtex-II Pro is a FPGA family which is collection different device sizes and package options with a common architecture. Boards that use FPGAs are each unique implementations with a fixed set of features that the FPGA design most conform to or it won't work. The Xilinx XUP2VP board and your IO constraints have a couple of problems: 1) G15/F15 are connected on the board with a 100 ohm termination resistor When you said that you "gave" a signal to G15 and "took" it from F15 the 100 ohm resistor provided a pass through of the signal and the FPGA did not need to be involved. It isn't clear what is actually happening on your setup. If the input did resolve to a 0/1 in the FPGA then the output should drive the same value a few nanosconds later. This would lead to some contention during this period and the output waveform would not be clean. Your oscilloscope may be filtering this out due to the short duration. 2) The VCCO for the banks that you are using are 3.3V Bank 1 (F16/G16) and bank 3 (AC6) both have VCCO levels of 3.3V, but your UCF file has defined these IOs as LVCMOS25. The output should still be working, but without the correct drive strengths and levels. The input functionality will depend on the voltage that is present on the pin. It may resolve or it may not. You haven't said anything about the actual device that you are trying to interface with so I don't know what levels it is expecting and putting out. If the levels are correct then nothing will work. There is the possibilities that you have are not probing the correct pin on the connector. I would suggest that you try outputting the system clock to the desired pin to verify that you are probing/ connecting the right pin. Ed McGettigan -- Xilinx Inc.
