Nios II Going Live...

Tomorrow is the big Nios II launch date, but info is already going up....

www.altera.com

http://www.fpgajournal.com/articles/20040518_nios2.htm


Full 32bit. 2X-4X faster than Nios I and starts at only 500 LE's.  New IDE.
New Compact Flash and other periferals.... Can't wait to get a hold of it.

Ken

It seems that Altera has created a MicroBlaze as well.
They have finally realized that a FPGA based soft processor should have
- 32 bit ISA
- 32 registers
- 3 operand instruction format
- JTAG based HW debugging
- HW divider

The weird register window mechanism from NIOS (is it called NIOS1 now?) 
didn't work well in embedded processing markets.

G�ran Bilski


Kenneth Land wrote:

>Tomorrow is the big Nios II launch date, but info is already going up....
>
>www.altera.com
>
>http://www.fpgajournal.com/articles/20040518_nios2.htm
>
>
>Full 32bit. 2X-4X faster than Nios I and starts at only 500 LE's.  New IDE.
>New Compact Flash and other periferals.... Can't wait to get a hold of it.
>
>Ken
>
>
>  
>

Goran Bilski wrote:
> It seems that Altera has created a MicroBlaze as well.
> They have finally realized that a FPGA based soft processor should have
> - 32 bit ISA
> - 32 registers
> - 3 operand instruction format
> - JTAG based HW debugging
> - HW divider
> 
> The weird register window mechanism from NIOS (is it called NIOS1 now?) 
> didn't work well in embedded processing markets.

I did hear that NIOS II was quite close to the MIPs CPU in 
structure/mindset....
-jg

"Jim Granville" <no.spam@designtools.co.nz> schreef in bericht
news:mPEqc.2994$FN.310885@news02.tsnz.net...
> Goran Bilski wrote:
> > It seems that Altera has created a MicroBlaze as well.
> > They have finally realized that a FPGA based soft processor should have
> > - 32 bit ISA
> > - 32 registers
> > - 3 operand instruction format
> > - JTAG based HW debugging
> > - HW divider
> >
> > The weird register window mechanism from NIOS (is it called NIOS1 now?)
> > didn't work well in embedded processing markets.
>
> I did hear that NIOS II was quite close to the MIPs CPU in
> structure/mindset....

And I heared that the old NIOS was a SPARC structure.

"Goran Bilski" <goran@xilinx.com> wrote in message
news:c8f3f0$cfe1@cliff.xsj.xilinx.com...
> It seems that Altera has created a MicroBlaze as well.
> They have finally realized that a FPGA based soft processor should have
> - 32 bit ISA
> - 32 registers
> - 3 operand instruction format
> - JTAG based HW debugging
> - HW divider
>
> The weird register window mechanism from NIOS (is it called NIOS1 now?)
> didn't work well in embedded processing markets.
>
> G&#4294967295;ran Bilski
>
>


Aren't we lucky to have both X and A?  It's kind of like Intel and AMD.
We'd still have 386 SX's if AMD weren't tight on Intel's heals.

It will be interesting to see where we wind up, but the jump from hardcore
to softcore processors is quantum leap IMO.  If the reality of NiosII comes
even remotely close to the shiny brochure then it will be a very significant
step forward.

Having worked with the NiosI for about a year now, I wouldn't discount the
NiosII hype too quickly.  NiosI is pretty close to its hype and the main
components of the II (IDE, smaller/faster, bootloader management, version
control, single JTAG connection for entire process) address most of my
issues.

One thing I hope is that using cache on the II doesn't incur the Fmax
penalty that it does on the I.

Hopefully we'll know soon.  Anybody know when the II upgrade kits will ship?

Ken

Goran Bilski <goran@xilinx.com> wrote in message news:<c8f3f0$cfe1@cliff.xsj.xilinx.com>...
> It seems that Altera has created a MicroBlaze as well.
> They have finally realized that a FPGA based soft processor should have
> - 32 bit ISA
> - 32 registers
> - 3 operand instruction format
> - JTAG based HW debugging
> - HW divider

Lol.. Because Xilinx invented RISC didn't they?
 
> The weird register window mechanism from NIOS (is it called NIOS1 now?) 
> didn't work well in embedded processing markets.

Well, you can hardly call it weird (at least one mainstream arch,
SPARC, uses it), and in the embedded space, Tensilica have no problems
selling their arch, which also features register windows.

If you really want to sling some mud, my favourite part is where they
talk about "Avoiding processor obsolescence"... Er, hasn't this has
just made NIOS obsolete? How long before they change their minds
again?

Fair play to them, I didn't really think too much of NIOS, but if they
really can push 200MHz with this, then I am impressed.

Cheers,
JonB

In article <e87b9ce8.0405190623.168bb823@posting.google.com>,
Jon Beniston <jon@beniston.com> wrote:
>> The weird register window mechanism from NIOS (is it called NIOS1 now?) 
>> didn't work well in embedded processing markets.
>
>Well, you can hardly call it weird (at least one mainstream arch,
>SPARC, uses it), and in the embedded space, Tensilica have no problems
>selling their arch, which also features register windows.

Just because it is used, doesn't mean its a good idea.  Register
windows suck.  Register windows reinvented (rotating register file
from the IA64 suck as well).

If you want fast function-call save/restore, observe that going into a
cache or memory, you often have a wide interface, so the cost of
writing 4 ALIGNED words is the same as writing one, and have aligned 4
or aligned 8 load/store instructions.  Remember the FPGA mantra: Wires
are cheap, switching the wires is expensive.

>If you really want to sling some mud, my favourite part is where they
>talk about "Avoiding processor obsolescence"... Er, hasn't this has
>just made NIOS obsolete? How long before they change their minds
>again?

Nah, because NIOS1 will still be around.  One of the great things
about soft-cores is they are a bit easier to keep "in production"
compared with a hard core.

>Fair play to them, I didn't really think too much of NIOS, but if they
>really can push 200MHz with this, then I am impressed.

Looking at the talk at FPGA on some of the arch tricks used to make
the ALU so short in NIOS-1, it might be possible.



-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

All,

If you can compile your code from c, who cares what the architecture is?

Sorry, but it really doesn't matter.

Speed, and ease of use are what counts in this business.

Apologies to processor architects, but unless you are doing a research 
project, hardly anyone cares anymore about these details.

At lunch the other day we were reminiscing about how the Z8000 never 
took off because they changed their architecture and instruction set 
completely from the Z80 and immediately alienated all of their customers 
(who were still programming in assembly language in those days).

Not like that anymore.

Austin

PS:  check out http://biz.yahoo.com/prnews/040518/sftu114_1.html


Nicholas C. Weaver wrote:

> In article <e87b9ce8.0405190623.168bb823@posting.google.com>,
> Jon Beniston <jon@beniston.com> wrote:
> 
>>>The weird register window mechanism from NIOS (is it called NIOS1 now?) 
>>>didn't work well in embedded processing markets.
>>
>>Well, you can hardly call it weird (at least one mainstream arch,
>>SPARC, uses it), and in the embedded space, Tensilica have no problems
>>selling their arch, which also features register windows.
> 
> 
> Just because it is used, doesn't mean its a good idea.  Register
> windows suck.  Register windows reinvented (rotating register file
> from the IA64 suck as well).
> 
> If you want fast function-call save/restore, observe that going into a
> cache or memory, you often have a wide interface, so the cost of
> writing 4 ALIGNED words is the same as writing one, and have aligned 4
> or aligned 8 load/store instructions.  Remember the FPGA mantra: Wires
> are cheap, switching the wires is expensive.
> 
> 
>>If you really want to sling some mud, my favourite part is where they
>>talk about "Avoiding processor obsolescence"... Er, hasn't this has
>>just made NIOS obsolete? How long before they change their minds
>>again?
> 
> 
> Nah, because NIOS1 will still be around.  One of the great things
> about soft-cores is they are a bit easier to keep "in production"
> compared with a hard core.
> 
> 
>>Fair play to them, I didn't really think too much of NIOS, but if they
>>really can push 200MHz with this, then I am impressed.
> 
> 
> Looking at the talk at FPGA on some of the arch tricks used to make
> the ALU so short in NIOS-1, it might be possible.
> 
> 
> 

In article <c8fsde$a5q1@cliff.xsj.xilinx.com>,
Austin Lesea  <austin@xilinx.com> wrote:
>All,
>
>If you can compile your code from c, who cares what the architecture is?
>
>Sorry, but it really doesn't matter.
>
>Speed, and ease of use are what counts in this business.
>
>Apologies to processor architects, but unless you are doing a research 
>project, hardly anyone cares anymore about these details.

I disagree on the register window front.  It is a pain if you are
doing garbage collectors (you have to flush the windows), but more
importantly, it DOES impact performance.
-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

Goran Bilski <goran@xilinx.com> wrote in message news:<c8f3f0$cfe1@cliff.xsj.xilinx.com>...
> It seems that Altera has created a MicroBlaze as well.
> They have finally realized that a FPGA based soft processor should have
> - 32 bit ISA
> - 32 registers
> - 3 operand instruction format
> - JTAG based HW debugging
> - HW divider
> 
> The weird register window mechanism from NIOS (is it called NIOS1 now?) 
> didn't work well in embedded processing markets.
> 
> G&#4294967295;ran Bilski

Ouch! I don't want to get into any marketing debates or flame wars,
but I feel that inaccurate descriptions of the product I'm familiar
with should be called out:

- Nios I had a 16-bit ISA. You are correct sir.
- Nios I had 32 registers per window (that is, per context), and a
compiler option to make it a flat 32 registers (that has been in the
kit for a couple years now). You are again correct that Nios II has a
flat 32 registers.
- Nios I had JTAG-based HW & SW debugging (for some time now!)
- Nios I had a hardware divider custom instruction (in the kit!) that
in two mouse clicks and a documented compiler switch had HW divides
implemented.

And lest we forget:
- Avalon (off-chip memory at decent performance, anyone?)
- SOPC Builder. 
- A happy user-experience implementing systems.

Regards,

Jesse Kempa
Altera Corp.
jkempa at altera dot com