Hopefully the size of your paycheck will be the third possible size, not the first ;-) Eric Crabill wrote:> Goran Bilski wrote: > > > > There should only be different 3 numbers used as sizes, > > 0, 1 or infinity. Any other number will creating barriers > > that will be reach and have impacts on the system. > > I'm headed over to payroll right now! > > Eric-- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759
Nios II Going Live...
Started by ●May 19, 2004
Reply by ●May 19, 20042004-05-19
Reply by ●May 20, 20042004-05-20
Austin Lesea wrote:> Tim, > > Low blow. > > S3 shipped a lot of parts last quarter. A whole lot of parts.Sorry Austin, Just asked, for the xc3s400-fg456 I can get now ces samples. Probably I can get parts in 14 weeks, so I stay with spartanII.> No one expected the product to gather that many orders that fast. Even > the optomists among us were made to look like pessimistic fools. > > If we would have only believed our own sales pitch that S3 was a better > deal than an ASIC in volume (which it is), we might have been at least > partially prepared.So, xilinx did something right, and it is wrong again ? ;-)> Austin > > Tim wrote: > >> "Austin Lesea" wrote >> >>> At lunch the other day we were reminiscing about how the Z8000 never >>> took off because they changed their architecture and instruction set >>> completely from the Z80 and immediately alienated all of their customers >>> (who were still programming in assembly language in those days). >> Not quite getting it into production may have troubled some customers... >> >>> Not like that anymore. >> The Spartan-3 of its day ;-)
Reply by ●May 20, 20042004-05-20
ES, Yes. Xilinx just can not do anything at all "right." The most FPGAs shipped in the history of FPGAs (Virtex family), the only FPGA with embedded processors, the first FPGA ever with 10 Gbs transceivers, lowest interrupt latency of any soft processor core(and even better than most hard processors), 40% speed improvement in our tools, over 250K seats of software shipped, XCell Magazine with a subscription larger than the premier electronics mag...... Such a bummer, I guess we must just keep striving to be better and better! Austin
Reply by ●May 20, 20042004-05-20
In deeply embedded systems (i.e. no RTOS), the use of the windowed registers is extremely useful due to its speed. When you start using the processor in applications that have an RTOS, it's a different story. Each time you have to do a context switch, unless the RTOS is really clever, you have to save out the whole set of registers associated with the task that is getting swapped out and read in the set of registers for the task that is getting swapped back in. Initially soft-core microprocessors on FPGAs were used as simple control processors by the HW engineers in place of state-machines. So only rarely did someone want to run an OS on them. But as they have gained more acceptance, engineers want the same tools that other microprocessors provide. Having a compiler option allowed you to choose between using the windowed registers vs. a flat register. With Nios II we optimized for size and speed, and the architecture we chose did not use the register windows. -Joel- Jim Granville <no.spam@designtools.co.nz> wrote in message news:<43Qqc.3057$FN.324468@news02.tsnz.net>...> Goran Bilski wrote: > > > It's creating weird situation in embedding processing where you reach > > the limit of the window. > > There should only be different 3 numbers used as sizes, 0, 1 or infinity. > > Any other number will creating barriers that will be reach and have > > impacts on the system. > > On reaching the limit of the register window, you have a big chunk of > > data to save and load which isn't nice to have when you need to have a > > deterministic system. > > I'm lost - since the register count is finite at around 32 in most RISC > designs, how does removing a feature improve the situation ?. > > I don't know the specific NIOS details, but Register window/Frame > Pointer/Register Bank select schemes have been around for years, and > can greatly help code density and reaction speed if done properly. > I think sparc had a clever partial frame pointer, that allowed some > registers to carry calling/return parameters, and some as local variables. > The compiler needs 'to be on its toes', but that's a SW > housekeeping issue. > Another nice feature of register frame pointers, is if you are > uncomfortable with them, you can just ignore it, and you have > a 'vanilla RISC' core. > > -jg
Reply by ●May 20, 20042004-05-20
Joel A. Seely wrote:> In deeply embedded systems (i.e. no RTOS), the use of the windowed > registers is extremely useful due to its speed. When you start using > the processor in applications that have an RTOS, it's a different > story. Each time you have to do a context switch, unless the RTOS is > really clever, you have to save out the whole set of registers > associated with the task that is getting swapped out and read in the > set of registers for the task that is getting swapped back in.The problem here is because you accept/target a 'less than really clever' RTOS, you also compromise the available peak performance.> > Initially soft-core microprocessors on FPGAs were used as simple > control processors by the HW engineers in place of state-machines. So > only rarely did someone want to run an OS on them. But as they have > gained more acceptance, engineers want the same tools that other > microprocessors provide....but the first group have not 'gone away' ?> Having a compiler option allowed you to choose between using the > windowed registers vs. a flat register. With Nios II we optimized for > size and speed, and the architecture we chose did not use the register > windows.One advantage of a FPGA core is you CAN change it as tools evolve :) One path that appeals for embedded design, is the hyperthread/switched CPU approach, that is now appearing in mainstream MPU (and so tools will follow, over time ). eg Ubicom divide their newest CPU into (IIRC) 64 time slots, and tasks/processes can have N,M etc of those slots assigned. Result is good granularity of horsepower allocation, and very hard real-time performance. With a FPGA, you could assign the hard real time stuff to one Core, with register pointer features ON, and running the small, time paranoid code. Time muxed on the other core, you can run the softer-time stuff, on a RTOS, with register pointer features OFF. In this approach, you are really multiplexing at the slowest memory BUS pivot, rather than context thrashing a single, fast core. -jg
Reply by ●May 20, 20042004-05-20
Austin Lesea <austin@xilinx.com> wrote in message news:<c8im4g$cfc1@cliff.xsj.xilinx.com>...> ES, > > Yes. Xilinx just can not do anything at all "right." > > The most FPGAs shipped in the history of FPGAs (Virtex family), the only > FPGA with embedded processors, the first FPGA ever with 10 Gbs > transceivers, lowest interrupt latency of any soft processor core(and > even better than most hard processors), 40% speed improvement in our > tools, over 250K seats of software shipped, XCell Magazine with a > subscription larger than the premier electronics mag...... > > Such a bummer, I guess we must just keep striving to be better and better! > > AustinMr. Lesea, this is not a flame, but to correct an error in your statement: "the only FPGA with embedded processors" is far from the truth. The following come to mind immediately (I'm sure I'm forgetting several): - Nios & Excalibur (Introduced June, 2000, that was FOUR years ago, and a year ahead of the competition; my how time flies!) - QuickLogic - The company you just acquired (I'll leave my theories out of this post) All are processors on FPGAs. These are commercial offerings, there are numerous 3rd party & free cores out there too. Your comments on ISR latency can be debated if you like, but I won't get into it now; there is already a thread discussing the architectural pros & cons that affect this. Boy, all this stuff makes feel me like I did yesterday when a guy dropped in on me while surfing. Regards, Jesse Kempa Altera Corp. jkempa at altera dot com
Reply by ●May 20, 20042004-05-20
Austin Lesea wrote:> lowest interrupt latency of any soft processor core (and > even better than most hard processors)that must be red rag to a bull for john jackson and the other transputer folk. and why are there so many transputer people in fpgaland?
Reply by ●May 20, 20042004-05-20
"Joel A. Seely" <jseely@altera.com> wrote in message news:9bded7a8.0405200947.28b2d90c@posting.google.com...> In deeply embedded systems (i.e. no RTOS), the use of the windowed > registers is extremely useful due to its speed. When you start using > the processor in applications that have an RTOS, it's a different > story. Each time you have to do a context switch, unless the RTOS is > really clever, you have to save out the whole set of registers > associated with the task that is getting swapped out and read in the > set of registers for the task that is getting swapped back in. > > Initially soft-core microprocessors on FPGAs were used as simple > control processors by the HW engineers in place of state-machines. So > only rarely did someone want to run an OS on them. But as they have > gained more acceptance, engineers want the same tools that other > microprocessors provide. > > Having a compiler option allowed you to choose between using the > windowed registers vs. a flat register. With Nios II we optimized for > size and speed, and the architecture we chose did not use the register > windows. > > -Joel- > >Hi Joel, (trying to tune out the trolls here) I'm going to be porting what you call a "deeply embedded" interrrupt driven application from NiosI to NiosII shortly. Can you contrast the two in terms of interrupt latency? The app was originally developed on a dual coldfire system and I can say a single Cyclone based NiosI handles things very nicely. I'm looking forward to the new IDE and even more performance. Whatever the naysayer's say, Motorola is not sending me a new higher performance cpu to download to my *existing boards*. This is great stuff! TIA, Ken
Reply by ●May 20, 20042004-05-20
Jesse, Processors, plural. I'm still right. Austin Jesse Kempa wrote:> Austin Lesea <austin@xilinx.com> wrote in message news:<c8im4g$cfc1@cliff.xsj.xilinx.com>... > >>ES, >> >>Yes. Xilinx just can not do anything at all "right." >> >>The most FPGAs shipped in the history of FPGAs (Virtex family), the only >>FPGA with embedded processors, the first FPGA ever with 10 Gbs >>transceivers, lowest interrupt latency of any soft processor core(and >>even better than most hard processors), 40% speed improvement in our >>tools, over 250K seats of software shipped, XCell Magazine with a >>subscription larger than the premier electronics mag...... >> >>Such a bummer, I guess we must just keep striving to be better and better! >> >>Austin > > > Mr. Lesea, this is not a flame, but to correct an error in your > statement: > > "the only FPGA with embedded processors" is far from the truth. The > following come to mind immediately (I'm sure I'm forgetting several): > - Nios & Excalibur (Introduced June, 2000, that was FOUR years ago, > and a year ahead of the competition; my how time flies!) > - QuickLogic > - The company you just acquired (I'll leave my theories out of this > post) > > All are processors on FPGAs. These are commercial offerings, there are > numerous 3rd party & free cores out there too. > > Your comments on ISR latency can be debated if you like, but I won't > get into it now; there is already a thread discussing the > architectural pros & cons that affect this. > > Boy, all this stuff makes feel me like I did yesterday when a guy > dropped in on me while surfing. > > Regards, > > Jesse Kempa > Altera Corp. > jkempa at altera dot com
Reply by ●May 20, 20042004-05-20
Austin Lesea wrote:> > ES, > > Yes. Xilinx just can not do anything at all "right." > > The most FPGAs shipped in the history of FPGAs (Virtex family), the only > FPGA with embedded processors, the first FPGA ever with 10 Gbs > transceivers, lowest interrupt latency of any soft processor core(and > even better than most hard processors), 40% speed improvement in our > tools, over 250K seats of software shipped, XCell Magazine with a > subscription larger than the premier electronics mag...... > > Such a bummer, I guess we must just keep striving to be better and better!I am just curious Austin, do you think this message helped either you or Xilinx? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
