Hi all, I've downloaded from the site in object a model of a usb3300 chip (usb2.0 otg transceiver) because I wanted to simulate the behaviour....I'm trying to develop an ulpi wrapper and have a behavioural model of the transceiver should save me a lot of time.... Unfortunately it seems not working at all...or I'm not compiling and simulating it in the right way. I use modelsim 6.5 se...I compiled using vhdl-93 and with vital2000 support...at least it should be.... Anyway...I'm forced to compile one file at time otherwise I get strange compilation errors and, when I start a simulation, I get a sigsegv on VitalPathDelay01Z...mmh I don't know where to start from....I'm considering to give up... :-( Any help will be very appreciated... If somebody want to try to use the package and verify.. it can be downloaded from http://www.freemodelfoundry.com/fmf_models/proc/usb3300_20081015.tar.gz a testebench is provided inside...it should be only compiled and simulated but for me became a black hole... Thanks in advance Carlo --------------------------------------- Posted through http://www.FPGARelated.com
Free Model Foundry USB3300
Started by ●April 20, 2011
Reply by ●April 20, 20112011-04-20
Nobody never used fmf models....please any help.... Carlo --------------------------------------- Posted through http://www.FPGARelated.com
Reply by ●April 20, 20112011-04-20
On Apr 20, 6:03=A0am, "carlob" <carlo.beccia@n_o_s_p_a_m.n_o_s_p_a_m.libero.it> wrote:> Nobody never used fmf models....please any help.... > > Carlo =A0 =A0 =A0If you want specific help, you should ask more specific questions. Simply saying things like 'I get strange compilation errors' or 'I get a sigsegv on VitalPathDelay01Z' are of no help to anyone except the limited audience that may have used that specific part. What you describe though seems like something more general which if you were to list what error messages you actually get would be of more help. Most people do not want to do all your work for you. Somewhat coincidentally, I can say that I have compiled that particular model without any problems and have at least started a sim with a testbench that instantiates that model...whether or not it correctly models the part I can't say other than the clock output does work. Kevin Jennings
Reply by ●April 21, 20112011-04-21
Thank you for the reply....no..I don't want that someone do work in my place...I'm doing this in my spare time....but I'm not able to do it...probably because I don't understand the error... Anyway I know that is terribly difficul to help someone without having had exactly the same problem...that's why I searched for someone that used the component...thank you for your help... You told me that you were able to compile correctly...I can tell you steps that I have followed to accomplish a compilation and you can check if I'm right..ok?? I create a new library called fmf with the fmf library files (only two are needed conversions.vhd and gen_utils.vhd). I compile with -93 version of compiler...no problems here... Then I map this library for compiling all files in src directory (test_pkg.vhd test_code.vhd test_bfm.vhd usb3300.vhd testbench_usb3300_vhdl.vhd in this order always with -93). At first I receive errors because it claims that test_code.vhd and test_bfm.vhd cannot see package work.test_pkg... It is strange in my opinion...it is the first file I compiled, but I notice that, under library work, test_pkg is the only library actually compiled... From here (with test_pkg already compiled) start a new compilation...now everything is ok...all is compiled well...no error... Ii is correct??? In your opinion I'm doing something wrong?? That's first time I saw a thing like that... Another way that I found effective to accomplish a right compilation here is to compile each file individually..... Anyway everything is compiled now...but I'm not sure if I'm doing something wrong... Problems start when I try to simulate..... I had different problems on different tries...(if I remember well because I don't have modelsim here).... Yesterday night I first compiled the sdf with sdfcom then I tried to launch a simulation with -sdftyp /dut=path_to_compiled_sdf without luck... Modelsim complains that: Failed to find INSTANCE dut (that is present in testbench and in sdf with tag INSTANCE...file usb3300_vhdl.sdf line 15)...after that SIGSEGV....I checked also the modelsim user guide...for me I'm doing ok...but doesn't work...if you look at testbench_usb3300_vhdl.vhd and usb3300_vhdl.sdf you can confirm that dut is the instance to which sdf refers and it is the name of instance of component usb3300 in testbench... If I compile checking to ignore sdf warnings and to translate errors in warnings I can start the simulation (obviuosly) but when I run it I receive a SIGSEGV...on line 2042 of usb3300.vhd....VitalPathDelay01Z... I think that the error is mainly in parsing the sdf file....generics for vital are not recognized well and crash...but I'm not so expert in timing simulation.... I don't know if I'm doing well...probably you can tell me If you did the same or not.... Maybe...there could be also an issue with my installation of modelsim...even if I tried to simulate with other old project and everyting seems working fine... Tonight I will try again and I will be more precise... Thank you Carlo>On Apr 20, 6:03=A0am, "carlob" ><carlo.beccia@n_o_s_p_a_m.n_o_s_p_a_m.libero.it> wrote: >> Nobody never used fmf models....please any help.... >> >> Carlo =A0 =A0 =A0 > >If you want specific help, you should ask more specific questions. >Simply saying things like 'I get strange >compilation errors' or 'I get a sigsegv on VitalPathDelay01Z' are of >no help to anyone except the limited audience that may have used that >specific part. What you describe though seems like something more >general which if you were to list what error messages you actually get >would be of more help. Most people do not want to do all your work >for you. > >Somewhat coincidentally, I can say that I have compiled that >particular model without any problems and have at least started a sim >with a testbench that instantiates that model...whether or not it >correctly models the part I can't say other than the clock output does >work. > >Kevin Jennings >--------------------------------------- Posted through http://www.FPGARelated.com
Reply by ●April 21, 20112011-04-21
Hi all,
to be more precise:
create a new library work:
vlib work
vmap work work
Compile gen_utils.vhd and conversions.vhd (fmf library):
vcom -reportprogress 300 -work work {C:/usb3300/src/fmf/gen_utils.vhd}
vcom -reportprogress 300 -work work {C:/usb3300/src/fmf/conversions.vhd}
in modelsim.ini I have set VHDL93 = 93
No problem till here....
Now start with usb3300:
change drectory to usb3300/src
create a new library work:
vlib work
vmap work work
map the previous library as fmf:
vmap fmf {C:/usb3300/src/fmf/work}
Compile files in src (in modelsim.ini I have set VHDL93 = 93):
vcom -reportprogress 300 -work work {C:/usb3300/src/test_pkg.vhd}
vcom -reportprogress 300 -work work {C:/usb3300/src/test_code.vhd}
vcom -reportprogress 300 -work work {C:/usb3300/src/test_bfm.vhd}
vcom -reportprogress 300 -work work {C:/usb3300/src/usb3300.vhd}
vcom -reportprogress 300 -work work
{C:/usb3300/src/testbench_usb3300_vhdl.vhd}
Till now...everything is fine....
Then I compiled usb3300_vhdl.sdf with sdfcom
sdfcom -typdelays usb3300_vhdl.sdf com_usb3300_vhdl.sdf
obtaining com_usb3300_vhdl.sdf
Start simulation:
vsim -sdftyp {/dut=C:/usb3300/src/com_usb3300_vhdl.sdf} -t ps
work.testbench_usb3300_vhdl
ERRORS:
# Loading std.standard
# ** INTERNAL ERROR: pkgref: export lookup failed.
# Loading instances from C:/usb3300/src/com_usb3300_vhdl.sdf
# ** Error: (vsim-SDF-3250) usb3300_vhdl.sdf(17): Failed to find INSTANCE
'dut'.
# ** Error: (vsim-SDF-3894) : Errors occured in reading and resolving
instances from compiled SDF file(s).
# ** Fatal: (SIGSEGV) Bad handle or reference.
# Time: 0 ps Iteration: 0 Process:
/testbench_usb3300_vhdl/dut/behavior/d_out_pathdelay_gen__0/line__2042
File: C://usb3300/src/usb3300.vhd
# FATAL ERROR while loading design
Then I Tried:
# Loading std.standard
# ** INTERNAL ERROR: pkgref: export lookup failed.
# Loading instances from C:/usb3300/src/com_usb3300_vhdl.sdf
# Loading timing data from C:/usb3300/src/com_usb3300_vhdl.sdf
# ** Fatal: (SIGSEGV) Bad handle or reference.
# Time: 0 ps Iteration: 0 Process:
/testbench_usb3300_vhdl/dut/behavior/d_out_pathdelay_gen__0/line__2042
File: C:/usb3300/src/usb3300.vhd
# FATAL ERROR while loading design
As you can see now the instance is resolved but modelsim SIGSEGV again. The
same result if I use the sdf not previously compiled...
At the end I tried again by compiling after disabling all possible checks
and optimizations in modelsim.ini:
Explicit = 0 NoDebug = 0 CheckSynthesis = 0 NoVitalCheck = 1 Optimize_1164
= 0
NoVital = 1 Quiet = 0 Show_source = 0 DisableOpt = 0
Everything is fine....now the simulation...
Failed to find INSTANCE 'dut'as before..changing instance to / seems
ok...layout change to simulate
# vsim -sdftyp {/=C:/usb3300/src/com_usb3300_vhdl.sdf} -t ps -novopt
work.testbench_usb3300_vhdl
# Loading std.standard
# ** INTERNAL ERROR: pkgref: export lookup failed.
# Loading instances from C:/Documents and
Settings/Carlo/Desktop/USB/EVB3300/usb3300/src/com_usb3300_vhdl.sdf
# Loading timing data from C:/Documents and
Settings/Carlo/Desktop/USB/EVB3300/usb3300/src/com_usb3300_vhdl.sdf
# ** Note: (vsim-3587) SDF Backannotation Successfully Completed.
# Time: 0 ps Iteration: 0 Region: /testbench_usb3300_vhdl File:
C:/usb3300/src/testbench_usb3300_vhdl.vhd
but after run
run
# ** Note: -------------------------------------------------------------
# Time: 0 ps Iteration: 0 Instance: /testbench_usb3300_vhdl
# ** Note: -------------POSITIVE, POWER UP------------------------------
# Time: 0 ps Iteration: 0 Instance: /testbench_usb3300_vhdl
# ** Fatal: (SIGSEGV) Bad handle or reference.
# Time: 0 ps Iteration: 0 Process:
/testbench_usb3300_vhdl/dut/behavior/nxt_out_pathdelay File:
C:/usb3300/src/usb3300.vhd
# Fatal error in Process nxt_out_pathdelay at C:/usb3300/src/usb3300.vhd
line 2091
#
# HDL call sequence:
# Stopped at C:/usb3300/src/usb3300.vhd 2091 Process nxt_out_pathdelay
I'm still thinking that I'm using the sdf file in an uncorrect way...anyway
I don't find the right way...
I know t post is very long...I'm sorry....
Hope kevin or someone else can help me
Thank you very much
Carlo
>On Apr 20, 6:03=A0am, "carlob"
><carlo.beccia@n_o_s_p_a_m.n_o_s_p_a_m.libero.it> wrote:
>> Nobody never used fmf models....please any help....
>>
>> Carlo =A0 =A0 =A0
>
>If you want specific help, you should ask more specific questions.
>Simply saying things like 'I get strange
>compilation errors' or 'I get a sigsegv on VitalPathDelay01Z' are of
>no help to anyone except the limited audience that may have used that
>specific part. What you describe though seems like something more
>general which if you were to list what error messages you actually get
>would be of more help. Most people do not want to do all your work
>for you.
>
>Somewhat coincidentally, I can say that I have compiled that
>particular model without any problems and have at least started a sim
>with a testbench that instantiates that model...whether or not it
>correctly models the part I can't say other than the clock output does
>work.
>
>Kevin Jennings
>
---------------------------------------
Posted through http://www.FPGARelated.com
Reply by ●April 21, 20112011-04-21
On Thu, 21 Apr 2011 16:08:06 -0500, "carlob" wrote:>Start simulation: >vsim -sdftyp {/dut=C:/usb3300/src/com_usb3300_vhdl.sdf} -t ps > work.testbench_usb3300_vhdlIt seems very unlikely that the full hierarchical path to the module is "/dut". Load the simulation without the SDF option at all, and look in the GUI to see what ModelSim thinks is the name of the DUT instance. It's probably something like /testbench_usb3300_vhdl/dut (that appears in one of the error messages). Put that into your -sdftyp option in place of /dut and things will probably go better. -- Jonathan Bromley
Reply by ●April 21, 20112011-04-21
Hi jonathan......thank you very much...(If I remember well I've read in the
user manual that is not ever needed to specify the top entity)...anyway
that's the result of a try....
vsim -sdftyp
{/testbench_usb3300_vhdl/dut=C:/usb330/src/com_usb3300_vhdl.sdf} -t ps
work.testbench_usb3300_vhdl
# vsim -sdftyp
{/testbench_usb3300_vhdl/dut=C:/usb3300/src/com_usb3300_vhdl.sdf} -t ps
work.testbench_usb3300_vhdl
# Loading std.standard
# ** INTERNAL ERROR: pkgref: export lookup failed.
# ** INTERNAL ERROR: pkgref: export lookup failed.
# ** INTERNAL ERROR: pkgref: export lookup failed.
# ** INTERNAL ERROR: pkgref: export lookup failed.
# ** INTERNAL ERROR: pkgref: export lookup failed.
# ** INTERNAL ERROR: pkgref: export lookup failed.
# ** INTERNAL ERROR: pkgref: export lookup failed.
# ** INTERNAL ERROR: pkgref: export lookup failed.
# ** INTERNAL ERROR: pkgref: export lookup failed.
# ** INTERNAL ERROR: pkgref: export lookup failed.
# ** INTERNAL ERROR: pkgref: export lookup failed.
# ** INTERNAL ERROR: pkgref: export lookup failed.
# ** INTERNAL ERROR: pkgref: export lookup failed.
# Loading ieee.std_logic_1164(body)
# Loading std.textio(body)
# Loading ieee.vital_timing(body)
# Loading ieee.vital_primitives(body)
# Loading fmf.gen_utils(body)
# Loading fmf.conversions(body)
# Loading work.test_pkg(body)
# Loading work.test_code(body)
# Loading work.ulpi_pkg(body)
# Loading work.usb_pkg(body)
# Loading work.testbench_usb3300_vhdl(vhdl_behavioral)
# Loading work.usb3300(vhdl_behavioral)
# Loading work.test_bfm(test_bfm_hdl)
# Loading instances from C:/usb3300/src/com_usb3300_vhdl.sdf
# ** Error: (vsim-SDF-3250) usb3300_vhdl.sdf(17): Failed to find INSTANCE
'dut'.
# ** Error: (vsim-SDF-3894) : Errors occured in reading and resolving
instances from compiled SDF file(s).
# Error loading design
The only way to let it start is to specify -sdftyp /=sdf file name...but
then the simualtion SIGSEGV...and it is not correct...the right parameter
should be, as you suggest, /testbench_usb3300_vhdl/dut....
It seems impossible that for kevin the model worked without problems....
..any hint is welcome...
It's late now here..I'm going to sleep...if I will have more options I will
try again tomorrow night...
Thank you again
Carlo
>On Thu, 21 Apr 2011 16:08:06 -0500, "carlob" wrote:
>
>>Start simulation:
>>vsim -sdftyp {/dut=C:/usb3300/src/com_usb3300_vhdl.sdf} -t ps
>> work.testbench_usb3300_vhdl
>
>It seems very unlikely that the full hierarchical path
>to the module is "/dut". Load the simulation without the SDF
>option at all, and look in the GUI to see what ModelSim thinks
>is the name of the DUT instance. It's probably something like
>/testbench_usb3300_vhdl/dut (that appears in one of the error
>messages). Put that into your -sdftyp option in place of /dut
>and things will probably go better.
>--
>Jonathan Bromley
>
---------------------------------------
Posted through http://www.FPGARelated.com
Reply by ●April 22, 20112011-04-22
>"carlob" wrote in message >news:F-adnR6vhetVMi3QnZ2dnUVZ_h2dnZ2d@giganews.com... ># Loading std.standard ># ** INTERNAL ERROR: pkgref: export lookup failed.This looks like a Modelsim bug. I ran the design on DE 10.0a and it seems OKish.># Loading instances from C:/usb3300/src/com_usb3300_vhdl.sdf ># ** Error: (vsim-SDF-3250) usb3300_vhdl.sdf(17): Failed to find INSTANCE >'dut'.I get the same error, looks like the SDF file is not correct or not compatible with Modelsim.>The only way to let it start is to specify -sdftyp /=sdf file name...but >then the simualtion SIGSEGV...and it is not correct...the right parameter >should be, as you suggest, /testbench_usb3300_vhdl/dut.... >It seems impossible that for kevin the model worked without problems....As Jonathan suggested try running it without the sdf file, you should get something like: run 10 ms # ** Note: ------------------------------------------------------------- # Time: 0 ps Iteration: 0 Instance: /testbench_usb3300_vhdl # ** Note: -------------POSITIVE, POWER UP------------------------------ # Time: 0 ps Iteration: 0 Instance: /testbench_usb3300_vhdl # ** Note: RECEIVED RX CMD = d"40" # Time: 3500091070 ps Iteration: 3 Instance: /testbench_usb3300_vhdl # ** Note: -------------POWER UP DONE----------------------------------- # Time: 3500091070 ps Iteration: 3 Instance: /testbench_usb3300_vhdl # ** Note: ------------------------------------------------------------- # Time: 3500091070 ps Iteration: 3 Instance: /testbench_usb3300_vhdl # ** Note: ------------------------------------------------------------- # Time: 3500091070 ps Iteration: 3 Instance: /testbench_usb3300_vhdl # ** Note: -------------TEST 1------------------------------------------ # Time: 3500091070 ps Iteration: 3 Instance: /testbench_usb3300_vhdl # ** Note: POSITIVE, after power up, Link resets PHY by setting the reset bit in the Function control register. # Time: 3500091070 ps Iteration: 3 Instance: /testbench_usb3300_vhdl # ** Warning: *usb3300 HOLD High VIOLATION ON DIn(...) WITH RESPECT TO CLKOUT; # Expected := 1 ns; Observed := 0 ns; At : 3500274.33 ns # Time: 3500274330 ps Iteration: 3 Region: /testbench_usb3300_vhdl/DUT/Behavior # ** Warning: *usb3300: simulation may be inaccurate due to timing violations # Time: 3500274330 ps Iteration: 3 Region: /testbench_usb3300_vhdl/DUT/Behavior # ** Note: -------------END OF TEST 1----------------------------------- .. # ** Note: -------------END OF TEST 15----------------------------------- # Time: 17256729708 ps Iteration: 2 Instance: /testbench_usb3300_vhdl # ** Note: ------------------------------------------------------------- # Time: 17256729708 ps Iteration: 2 Instance: /testbench_usb3300_vhdl # ** Note: Test ended without errors # Time: 17256729708 ps Iteration: 2 Instance: /testbench_usb3300_vhdl I would try to contact the creator ( n�porobic@hdl�dh.com?) and see if he can help you out. I am sure he would appreciate the feedback, Good luck, Hans www.ht-lab.com>..any hint is welcome... > >It's late now here..I'm going to sleep...if I will have more options I will >try again tomorrow night... > >Thank you again >Carlo >
Reply by ●April 22, 20112011-04-22
Hi Hans, yes..I will try that too....at the moment I tried to contatct Richard Munden: munden@freemodelfoundry.com the author of the book: ASIC and FPGA Verification: A Guide to Component Modeling (Systems on Silicon)...he seems to be very involved in free model foundry...but without any luck...no answer... Maybe I want to try to reinstall modelsim...the error on pgref sounds bad to me and I've read on internet that someone with this kind of problems solved with a full reinstallation...otherwise is very strange.... Thank you anyway for reply....> >I would try to contact the creator ( n�porobic@hdl�dh.com?) and see ifhe>can help you out. I am sure he would appreciate the feedback, > >Good luck, >Hans >www.ht-lab.com > > >>..any hint is welcome... >> >>It's late now here..I'm going to sleep...if I will have more options Iwill>>try again tomorrow night... >> >>Thank you again >>Carlo >> > >--------------------------------------- Posted through http://www.FPGARelated.com
Reply by ●April 22, 20112011-04-22
Hi Hans, thank you again...I'm sorry but I haven't read the first part of the answer....ok I will try without the sdf...I don't remenber well but probably I've already tried with the same result as before.... A good modelsim reinstall is needed....I'm ever more convinced that is a tool problem.... Thank you again Carlo> >>"carlob" wrote in message >>news:F-adnR6vhetVMi3QnZ2dnUVZ_h2dnZ2d@giganews.com... >># Loading std.standard >># ** INTERNAL ERROR: pkgref: export lookup failed. > >This looks like a Modelsim bug. I ran the design on DE 10.0a and it seems>OKish. > >># Loading instances from C:/usb3300/src/com_usb3300_vhdl.sdf >># ** Error: (vsim-SDF-3250) usb3300_vhdl.sdf(17): Failed to findINSTANCE>>'dut'. > >I get the same error, looks like the SDF file is not correct or not >compatible with Modelsim. > >>The only way to let it start is to specify -sdftyp /=sdf file name...but >>then the simualtion SIGSEGV...and it is not correct...the rightparameter>>should be, as you suggest, /testbench_usb3300_vhdl/dut.... >>It seems impossible that for kevin the model worked without problems.... > >As Jonathan suggested try running it without the sdf file, you should get>something like: > >run 10 ms ># ** Note: ------------------------------------------------------------- ># Time: 0 ps Iteration: 0 Instance: /testbench_usb3300_vhdl ># ** Note: -------------POSITIVE, POWER UP------------------------------ ># Time: 0 ps Iteration: 0 Instance: /testbench_usb3300_vhdl ># ** Note: RECEIVED RX CMD = d"40" ># Time: 3500091070 ps Iteration: 3 Instance: /testbench_usb3300_vhdl ># ** Note: -------------POWER UP DONE----------------------------------- ># Time: 3500091070 ps Iteration: 3 Instance: /testbench_usb3300_vhdl ># ** Note: ------------------------------------------------------------- ># Time: 3500091070 ps Iteration: 3 Instance: /testbench_usb3300_vhdl ># ** Note: ------------------------------------------------------------- ># Time: 3500091070 ps Iteration: 3 Instance: /testbench_usb3300_vhdl ># ** Note: -------------TEST 1------------------------------------------ ># Time: 3500091070 ps Iteration: 3 Instance: /testbench_usb3300_vhdl ># ** Note: POSITIVE, after power up, Link resets PHY by setting the reset>bit in the Function control register. ># Time: 3500091070 ps Iteration: 3 Instance: /testbench_usb3300_vhdl ># ** Warning: *usb3300 HOLD High VIOLATION ON DIn(...) WITH RESPECT TO >CLKOUT; ># Expected := 1 ns; Observed := 0 ns; At : 3500274.33 ns ># Time: 3500274330 ps Iteration: 3 Region: >/testbench_usb3300_vhdl/DUT/Behavior ># ** Warning: *usb3300: simulation may be inaccurate due to timing >violations ># Time: 3500274330 ps Iteration: 3 Region: >/testbench_usb3300_vhdl/DUT/Behavior ># ** Note: -------------END OF TEST 1----------------------------------- >.. ># ** Note: -------------END OF TEST 15----------------------------------- ># Time: 17256729708 ps Iteration: 2 Instance:/testbench_usb3300_vhdl># ** Note: ------------------------------------------------------------- ># Time: 17256729708 ps Iteration: 2 Instance:/testbench_usb3300_vhdl># ** Note: Test ended without errors ># Time: 17256729708 ps Iteration: 2 Instance:/testbench_usb3300_vhdl> >I would try to contact the creator ( n�porobic@hdl�dh.com?) and see ifhe>can help you out. I am sure he would appreciate the feedback, > >Good luck, >Hans >www.ht-lab.com > > >>..any hint is welcome... >> >>It's late now here..I'm going to sleep...if I will have more options Iwill>>try again tomorrow night... >> >>Thank you again >>Carlo >> > >--------------------------------------- Posted through http://www.FPGARelated.com
