ise 10.1 (Linux) contraints problem

Hello, all,

I'm using Xilinx Ise 10.1 on a Linux system, and ran into a crazy problem.
I took a previous design and stripped out a bunch of stuff to make a
skeleton of that project to test something, leaving over a bunch of pins
that became unused.  I then removed the unused pins from the top-level VHDL
file's port list, and removed those LOC definitions from my .ucf file.

Now, when I try to implement that, I get a bunch of messages that there were
constraints that didn't match a signal name.  I edited the .ucf file again,
deleted it from the project and re-added it, but it still finds these
constraints.  If I open the .ucf in the text editor, they are not there,
but if I open constraints in the constraint editor - port page, they do
show up.

Anybody know where these are coming from, or what I can do to refresh ise to
get rid of this stale data?

(There used to be a button to "remove implementation data" that would clear
out this sort of thing, but I can't find it in 10.1.)

Thanks,

Jon

>Hello, all,
>
>I'm using Xilinx Ise 10.1 on a Linux system, and ran into a crazy
problem.
>I took a previous design and stripped out a bunch of stuff to make a
>skeleton of that project to test something, leaving over a bunch of pins
>that became unused.  I then removed the unused pins from the top-level
VHDL
>file's port list, and removed those LOC definitions from my .ucf file.
>
>Now, when I try to implement that, I get a bunch of messages that there
were
>constraints that didn't match a signal name.  I edited the .ucf file
again,
>deleted it from the project and re-added it, but it still finds these
>constraints.  If I open the .ucf in the text editor, they are not there,
>but if I open constraints in the constraint editor - port page, they do
>show up.
>
>Anybody know where these are coming from, or what I can do to refresh ise
to
>get rid of this stale data?
>
>(There used to be a button to "remove implementation data" that would
clear
>out this sort of thing, but I can't find it in 10.1.)
>
>Thanks,
>
>Jon
>

Under Project menu, "Cleanup Project Files" might be what you are after.
Ensure that the [name].restore file is deleted, too.
	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Hi,

On 05/05/11 07:21 AM, Jon Elson wrote:
> Hello, all,
>
> I'm using Xilinx Ise 10.1 on a Linux system, and ran into a crazy problem.
> I took a previous design and stripped out a bunch of stuff to make a
> skeleton of that project to test something, leaving over a bunch of pins
> that became unused.  I then removed the unused pins from the top-level VHDL
> file's port list, and removed those LOC definitions from my .ucf file.
>
> Now, when I try to implement that, I get a bunch of messages that there were
> constraints that didn't match a signal name.  I edited the .ucf file again,
> deleted it from the project and re-added it, but it still finds these
> constraints.  If I open the .ucf in the text editor, they are not there,
> but if I open constraints in the constraint editor - port page, they do
> show up.
>
> Anybody know where these are coming from, or what I can do to refresh ise to
> get rid of this stale data?
>
> (There used to be a button to "remove implementation data" that would clear
> out this sort of thing, but I can't find it in 10.1.)
>
> Thanks,
>
> Jon
leave the GUI and use scripts, it never causes these problems!

/michael

RCIngham wrote:


> 
> Under Project menu, "Cleanup Project Files" might be what you are after.
> Ensure that the [name].restore file is deleted, too.
Great, thanks!  That option was staring me in the face.  All is working now.

Jon

Michael wrote:


> leave the GUI and use scripts, it never causes these problems!
Well, I'll have to learn how to do this.

I did use a command line to run promgen, as running it from the GUI crashes.

Jon

On May 5, 8:42=A0am, Jon Elson <el...@pico-systems.com> wrote:
> Michael wrote:
> > leave the GUI and use scripts, it never causes these problems!
>
> Well, I'll have to learn how to do this.
>
> I did use a command line to run promgen, as running it from the GUI crash=
es.
>
> Jon

Jon,

When you read the documentation for using the command line mode, you
will find that there are a number of files that are included
implicitly if found.  Most likely it was one of those files
(<projectname>.pcf is the most likely culprit) that was causing your
problem.

"Real engineers don't use GUIs",
RK

Hi,

On 05/05/11 05:42 PM, Jon Elson wrote:
> Michael wrote:
>
>
>> leave the GUI and use scripts, it never causes these problems!
> Well, I'll have to learn how to do this.
>
> I did use a command line to run promgen, as running it from the GUI crashes.
>
> Jon
To synth define PROJECT or replace with project name
xst -ifn ${PROJECT}.xst -ofn ${PROJECT}.log

You could use xflow to run the flow for P&R
xflow -p partname ${PROJECT}

There are probably even better ways that a are compatible with the GUI 
ising tcl I assume but I have not digged in to that, I am to old...or 
maybe not ;)

And then bitgen like you have done with promgen

You might need some config for bitgen

/michael

On 05/06/2011 12:52 AM, Michael wrote:
> Hi,
>
> On 05/05/11 05:42 PM, Jon Elson wrote:
>> Michael wrote:
>>
>>
>>> leave the GUI and use scripts, it never causes these problems!
>> Well, I'll have to learn how to do this.
>>
>> I did use a command line to run promgen, as running it from the GUI
>> crashes.
>>
>> Jon
> To synth define PROJECT or replace with project name
> xst -ifn ${PROJECT}.xst -ofn ${PROJECT}.log
>
> You could use xflow to run the flow for P&R
> xflow -p partname ${PROJECT}
>
> There are probably even better ways that a are compatible with the GUI
> ising tcl I assume but I have not digged in to that, I am to old...or
> maybe not ;)
>
> And then bitgen like you have done with promgen
>
> You might need some config for bitgen
OK, well I can probably dig the syntax out of the log files.  I had no 
idea it was that simple!

The Windows-fashioned text editor in ise is pretty awful, I usually use 
emacs.

I DO like the simulator, though.  MUCH easier to hop around in the 
hierarchy and bring up signals from various inner components of the 
design than Modelsim.  And, it automatically saves the signals on the 
screen for next time.

The promgen command line I got from a Xilinx article puts out the 
reverse bit ordering, so it wouldn't load.  I'll have to figure out what 
option sets it for the other ordering.  But, after I did the cleanup, 
the prom file formatter works from the gui.  I need to find out what I'm 
doing wrong that fouls up the management of vhdl files.
I put the files into a directory and edited them for the first cut there 
before setting up an ide project and adding the files to the project. 
This left several versions of files with the same name in the various 
levels of the directory, and I think that is what started this mess.

I think working both outside ide and inside it is most of the cause of 
the problem.

Jon

There have been an article in Xcell journal on how to use Xilinx tools
in command-line mode, if anybody is interested:

http://outputlogic.com/xcell_using_xilinx_tools/74_xperts_04.pdf


Thanks,
Evgeni

Hi,

On 05/06/11 11:16 PM, Jon Elson wrote:
> On 05/06/2011 12:52 AM, Michael wrote:
>> Hi,
>>
>> On 05/05/11 05:42 PM, Jon Elson wrote:
>>> Michael wrote:
>>>
>>>
>>>> leave the GUI and use scripts, it never causes these problems!
>>> Well, I'll have to learn how to do this.
>>>
>>> I did use a command line to run promgen, as running it from the GUI
>>> crashes.
>>>
>>> Jon
>> To synth define PROJECT or replace with project name
>> xst -ifn ${PROJECT}.xst -ofn ${PROJECT}.log
>>
>> You could use xflow to run the flow for P&R
>> xflow -p partname ${PROJECT}
>>
>> There are probably even better ways that a are compatible with the GUI
>> ising tcl I assume but I have not digged in to that, I am to old...or
>> maybe not ;)
>>
>> And then bitgen like you have done with promgen
>>
>> You might need some config for bitgen
> OK, well I can probably dig the syntax out of the log files. I had no
> idea it was that simple!
>
> The Windows-fashioned text editor in ise is pretty awful, I usually use
> emacs.
>
> I DO like the simulator, though. MUCH easier to hop around in the
> hierarchy and bring up signals from various inner components of the
> design than Modelsim. And, it automatically saves the signals on the
> screen for next time.
>
> The promgen command line I got from a Xilinx article puts out the
> reverse bit ordering, so it wouldn't load. I'll have to figure out what
> option sets it for the other ordering. But, after I did the cleanup, the
> prom file formatter works from the gui. I need to find out what I'm
> doing wrong that fouls up the management of vhdl files.
> I put the files into a directory and edited them for the first cut there
> before setting up an ide project and adding the files to the project.
> This left several versions of files with the same name in the various
> levels of the directory, and I think that is what started this mess.
>
> I think working both outside ide and inside it is most of the cause of
> the problem.
>
> Jon
Hi Jon, read the excelent article pointed out but outputlogic and go 
scripting. Next move is go linux perhaps starting on a Virtualbox 
installation on top of your Windows.

Good to hear that you use Emacs, have you installed the VHDL and Verilog 
extensions to emacs?