Why feedback clock in SDRAM controllers?

 > That's how important compensation of these delays are.

Really? Why do you think people care about the DLLs? Is it because they 
do not understand the importance of nanoscale timing?

Also, let me remind you, that in my question I pointed out that DCM 
feedbacks require that the FPGA-external feedback trace length matching 
the CLK trace length from FPGA to ram.

I keep reminding about this because do not see any reason for this 
design. Yet, I feel that it is a key and want anybody to explan.

You see, the dialog goes on:

A: The path delays must be taken into account these days. You know, they 
are important.
B: Ok. How this example design works?
A: Hm. Look at my first statement: things are very complicated now. We 
must take the delays into account.

This is an infinite loop. How can I break out of it and understand the 
design examples?



>
> If this is still not enough, maybe I can draw a diagram for you, but

yes, please

I agree. The first problem is that there will be FPGA-internal part of 
the loop, which increases this length. But the thing I want to know in 
the first place - why do we need the phase adjustment?

Which phase is adjusted? The DCM drives internal FFs, making them all in 
phase. The internal feedback is distributed via DCM-generated clock 
three and therefore matches the DCM-to-regs clock delay, making childern 
regs in-phase with the DCM input clock. Also, vendor tools can ensure 
that combinatorial logic delays are shorter than the period.

Now, the feedback goes through external path. The DCM input is in phase 
with the rest of FPGA system. The output is adjusted so that something 
distant (i.e. DRAM CLK input) is also in phase.

If this picture is right, I see no reason of this "phase matching". We 
cannot benefit from it because the tools ignore the fpga-external data 
paths. Even worse: the adjusted clock will arrive earlier than it would 
naturally. Normally, you would have data and clock changing 
simultaneouly (ok, clock raises in the middle of data slot) at FPGA 
outputs and, having the same external path delays, would arrive to SDRAM 
with low skew. I see that using DCM "adjustment" just breaks this 
natural "source synchronous" phase matching.