Hi, I'm very impressed with a J1 forth processor: http://excamera.com/sphinx/fpga-j1.html I'd like to use it to implement simple non-time critical control and debugging layer in my FPGA based DSP system. However to accomplish it I need to add possibility of interactive work via console connected either by UART or by JTAG. Has anybody tried to extend the J1 published in http://excamera.com/files/j1demo.tar.gz with possibility to interactively define new words and execute them? -- TIA & Regards, WZab
J1 forth processor in FPGA - possibility of interactive work?
Started by ●May 13, 2011
Reply by ●May 13, 20112011-05-13
There is a developer that just ported the Verilog version of the J1 processor to MyHDL. You might be able to leverage this work to easily make the modifications you mention. Posting to the MyHDL newsgroup might get a response. Regards, Chris Felton On 5/13/2011 7:34 AM, wzab wrote:> Hi, > > I'm very impressed with a J1 forth processor: http://excamera.com/sphinx/fpga-j1.html > I'd like to use it to implement simple non-time critical control and > debugging layer > in my FPGA based DSP system. > However to accomplish it I need to add possibility of interactive work > via console > connected either by UART or by JTAG. > Has anybody tried to extend the J1 published in http://excamera.com/files/j1demo.tar.gz > with possibility to interactively define new words and execute them? > -- > TIA& Regards, > WZab
Reply by ●May 13, 20112011-05-13
On May 13, 8:34=A0am, wzab <wza...@gmail.com> wrote:> Hi, > > I'm very impressed with a J1 forth processor:http://excamera.com/sphinx/f=pga-j1.html> I'd like to use it to implement simple non-time critical control and > debugging layer > in my FPGA based DSP system. > However to accomplish it I need to add possibility of interactive work > via console > connected either by UART or by JTAG. > Has anybody tried to extend the J1 published inhttp://excamera.com/files/=j1demo.tar.gz> with possibility to interactively define new words and execute them? > -- > TIA & Regards, > WZabPerhaps I don't understand what you are asking. The web page says there is a development system supported under gforth. "Cross compiler runs on Windows, Mac and Unix" Are you talking about extending the hardware design rather than new words in Forth? Oh, you mean "interactive" rather than batch mode... I get it. No, that would require a certain amount of work on run time code on the device as well as supporting code on the host system. You might take a look at Riscy Pygness. They have already done this for the ARM processor I believe. It might be easier to adapt that code to the J1 app than to reinvent (or recode) the wheel. Rick
Reply by ●May 14, 20112011-05-14
On May 14, 12:40=A0am, rickman <gnu...@gmail.com> wrote:> Perhaps I don't understand what you are asking. =A0The web page says > there is a development system supported under gforth. > > "Cross compiler runs on Windows, Mac and Unix" > > Are you talking about extending the hardware design rather than new > words in Forth?Well, this requires both extension of hardware (bidirectional port) and extension of Forth (compiler words in target system).> Oh, you mean "interactive" rather than batch mode... I get it. =A0No, > that would require a certain amount of work on run time code on the > device as well as supporting code on the host system. >On the host system the minicom for UART connection should be enough. For JTAG connection I have ready to use open solutions which may provide conectivity to such bidirectional port. https://groups.google.com/group/alt.sources/browse_thread/thread/38186c49dc= 5cf32e https://groups.google.com/group/alt.sources/browse_thread/thread/603ff14bdf= 020776> You might take a look at Riscy Pygness. =A0They have already done this > for the ARM processor I believe. =A0It might be easier to adapt that > code to the J1 app than to reinvent (or recode) the wheel.Well, what I expect to have is something like amforth ( http://amforth.sf.n= et ) but without implementing of ARM core in FPGA. In fact I have already succesfully experimented with similar solution based on 6809 core published on googlecode : http://code.google.com/p/rekonstrukt/ However the 6809 SoC is slow and resource hungry. J1 is both faster and simpler. BTW I have found, that the sources mentioned in the J1 paper as published under BSD license: http://excamera.com/files/j1.pdf and which may be downloaded via: svn co https://code.ros.org/svn/ros-pkg/stacks/camera_drivers/trunk/wge100_= camera_firmware/src/ are much better for experiments then j1demo.tar.gz (eg.they allow you to use different Ethernet PHY). WZab
Reply by ●May 14, 20112011-05-14
On May 14, 7:37=A0am, wzab <wza...@gmail.com> wrote:> On May 14, 12:40=A0am, rickman <gnu...@gmail.com> wrote: > > > Perhaps I don't understand what you are asking. =A0The web page says > > there is a development system supported under gforth. > > > "Cross compiler runs on Windows, Mac and Unix" > > > Are you talking about extending the hardware design rather than new > > words in Forth? > > Well, this requires both extension of hardware (bidirectional port) > and extension of Forth (compiler words in target system). > > > Oh, you mean "interactive" rather than batch mode... I get it. =A0No, > > that would require a certain amount of work on run time code on the > > device as well as supporting code on the host system. > > On the host system the minicom for UART connection should be enough. > For JTAG connection I have ready to use open solutions which may > provide conectivity > to such bidirectional port.https://groups.google.com/group/alt.sources/br=owse_thread/thread/3818...https://groups.google.com/group/alt.sources/brows= e_thread/thread/603f...> > > You might take a look at Riscy Pygness. =A0They have already done this > > for the ARM processor I believe. =A0It might be easier to adapt that > > code to the J1 app than to reinvent (or recode) the wheel. > > Well, what I expect to have is something like amforth (http://amforth.sf.=net> ) > but without implementing of ARM core in FPGA. > In fact I have already succesfully experimented with similar solution > based on > 6809 core published on googlecode :http://code.google.com/p/rekonstrukt/ > However the 6809 SoC is slow and resource hungry. J1 is both faster > and simpler. > > BTW I have found, that the sources mentioned in the J1 paper as > published under BSD > license:http://excamera.com/files/j1.pdf > and which may be downloaded via: > svn cohttps://code.ros.org/svn/ros-pkg/stacks/camera_drivers/trunk/wge100=_c...> are much better for experiments then j1demo.tar.gz (eg.they allow you > to use different Ethernet > PHY). > > WZabBTW, you might want to crosspost this to comp.lang.forth. Rick
Reply by ●May 14, 20112011-05-14
On May 14, 7:37=A0am, wzab <wza...@gmail.com> wrote:> On May 14, 12:40=A0am, rickman <gnu...@gmail.com> wrote: > > > Perhaps I don't understand what you are asking. =A0The web page says > > there is a development system supported under gforth. > > > "Cross compiler runs on Windows, Mac and Unix" > > > Are you talking about extending the hardware design rather than new > > words in Forth? > > Well, this requires both extension of hardware (bidirectional port) > and extension of Forth (compiler words in target system). > > > Oh, you mean "interactive" rather than batch mode... I get it. =A0No, > > that would require a certain amount of work on run time code on the > > device as well as supporting code on the host system. > > On the host system the minicom for UART connection should be enough. > For JTAG connection I have ready to use open solutions which may > provide conectivity > to such bidirectional port.https://groups.google.com/group/alt.sources/br=owse_thread/thread/3818...https://groups.google.com/group/alt.sources/brows= e_thread/thread/603f...> > > You might take a look at Riscy Pygness. =A0They have already done this > > for the ARM processor I believe. =A0It might be easier to adapt that > > code to the J1 app than to reinvent (or recode) the wheel. > > Well, what I expect to have is something like amforth (http://amforth.sf.=net> ) > but without implementing of ARM core in FPGA. > In fact I have already succesfully experimented with similar solution > based on > 6809 core published on googlecode :http://code.google.com/p/rekonstrukt/ > However the 6809 SoC is slow and resource hungry. J1 is both faster > and simpler. > > BTW I have found, that the sources mentioned in the J1 paper as > published under BSD > license:http://excamera.com/files/j1.pdf > and which may be downloaded via: > svn cohttps://code.ros.org/svn/ros-pkg/stacks/camera_drivers/trunk/wge100=_c...> are much better for experiments then j1demo.tar.gz (eg.they allow you > to use different Ethernet > PHY). > > WZabAt this point I can't say I understand what you are asking. Do you have something specific you are asking about or have you figured it out at this point? Rick
Reply by ●May 18, 20112011-05-18
> At this point I can't say I understand what you are asking. =A0Do you > have something specific you are asking about or have you figured it > out at this point? >The idea was to have a small but efficient CPU inside of FPGA which could be used to collect some debugging data (e.g. connected to my http://www.ise.pw.edu.pl/~wzab/fpgadbg tool) and also to control behavior of user IP core. Forth seems to be the best solution due to it's extendibility and possibility to work using simple link (serial or other). I've exchanged some e-mails with the developer who ported J1 to MyHDL and after this discussion I think, that the approach used in Riscy Pygness may be really the best solution. -- Thanks, Wojtek
Reply by ●May 18, 20112011-05-18
On May 18, 5:32=A0am, wzab <wza...@gmail.com> wrote:> The idea was to have a small but efficient CPU inside of FPGA which > could be used to collect some debugging data (e.g. connected > to myhttp://www.ise.pw.edu.pl/~wzab/fpgadbgtool) > and also to control behavior of user IP core. > Forth seems to be the best solution due to it's extendibility > and possibility to work using simple link (serial or other).I once saw a 3-word Forth, which consisted of only three words running on the target board: fetch, store and execute. Everything else was done on the host system and the three words were invoked over a serial link. You have two options: 1. Words compiled on the host run on the host, performing any I/O over the serial link. 2. Words compiled on the host run on the target after being uploaded. Do you need a CPU to implement the "three words" or can you use hardware? If you have a fast enough serial link (JTAG can be pretty fast), all you need is fetch and store in the FPGA and execute on the PC. An interesting interface option, while not as fast as SPI/JTAG, is I2C. Silabs CP2112 is a USB HID to I2C interface chip. A Forth (or Python or whatever) Windows app can talk to your I2C stuff with no drivers other than the built-in USB HID support. -Brad
Reply by ●May 18, 20112011-05-18
"Brad" <hwfwguy@gmail.com> wrote in message news:75de307b-6c91-46ed-9ee6-e2a57c5716a0@s41g2000prb.googlegroups.com... On May 18, 5:32 am, wzab <wza...@gmail.com> wrote:> > Forth seems to be the best solution due to it's extendibility > > and possibility to work using simple link (serial or other). > > I once saw a 3-word Forth, >Frank Sergeant's 3-instruction Forth: http://pygmy.utoh.org/forth.html Rod Pemberton
Reply by ●May 18, 20112011-05-18
On 5/18/11 6:16 AM, Brad wrote:> On May 18, 5:32 am, wzab<wza...@gmail.com> wrote: >> The idea was to have a small but efficient CPU inside of FPGA which >> could be used to collect some debugging data (e.g. connected >> to myhttp://www.ise.pw.edu.pl/~wzab/fpgadbgtool) >> and also to control behavior of user IP core. >> Forth seems to be the best solution due to it's extendibility >> and possibility to work using simple link (serial or other). > > I once saw a 3-word Forth, which consisted of only three words running > on the target board: fetch, store and execute. Everything else was > done on the host system and the three words were invoked over a serial > link. You have two options: > > 1. Words compiled on the host run on the host, performing any I/O over > the serial link. > 2. Words compiled on the host run on the target after being uploaded. > > Do you need a CPU to implement the "three words" or can you use > hardware? If you have a fast enough serial link (JTAG can be pretty > fast), all you need is fetch and store in the FPGA and execute on the > PC.Those three useful commands are necessary to support any kind of remote download or bootstrap regardless of language, but they certainly don't constitute anything resembling Forth. Most microprocessor boards come with this facility on board, usually in some form of ROM. JTAG is one way of doing it, although it also has other functions. Cheers, Elizabeth -- ================================================== Elizabeth D. Rather (US & Canada) 800-55-FORTH FORTH Inc. +1 310.999.6784 5959 West Century Blvd. Suite 700 Los Angeles, CA 90045 http://www.forth.com "Forth-based products and Services for real-time applications since 1973." ==================================================