Sporadic simulation result with modelsim

Hello all,

I struggle with an issue I can't understand the root cause.

When simulating my back annoted design with modelsim, I get unexpected
behavior when using a simulation step of 1ns, but no errors when using
a step of 1ps.

My design is running at 1MHz (so I expect a simulation step of 1ns to
be highly sufficient).
The part that is causing trouble is a wrapper around an SRAM instance
(it is an actel RAM512x18 component on an actel proasic3 FPGA).

I've got the exact same component instanciated in the exact same
wrapper simulating fine on an actel igloo FPGA. I am aware that place
and route may have produce significantly different results between the
two FPGAs and that having the design running smoothly on one FPGA
don't prove anything.

Still I can't figure out why modelsim would not simulate identically
using a 1ns or 1ps step.

Last but not least, I've got no warning from modelsim (no glitch
found).

If any of you have an idea of what could be happening there I would be
glad to ear it.

Regards

On 20 Jun., 12:12, JB <jb.dubois....@gmail.com> wrote:
> When simulating my back annoted design with modelsim, I get unexpected
> behavior when using a simulation step of 1ns, but no errors when using
> a step of 1ps.
>
> My design is running at 1MHz (so I expect a simulation step of 1ns to
> be highly sufficient).
> The part that is causing trouble is a wrapper around an SRAM instance
> (it is an actel RAM512x18 component on an actel proasic3 FPGA).

The selected technology knows delays below 1 ns, your clock frequency
is not everything to take into account.
Consider you have in clock tree between two register 2 buffer
difference with 100 ps delay each leading to a skew of 200 ps between
those registers and in datapath 1 cell with 500 ps delay.
Using 1ns resolution would lead to 2 ns skew vs 1 ns data which ends
up with 1 ns data before clock violation against 300 ps clock before
data when using 1 ps resolution.

regards Thomas

On 20 juin, 14:21, Thomas Stanka <usenet_nospam_va...@stanka-web.de>
wrote:
> On 20 Jun., 12:12, JB <jb.dubois....@gmail.com> wrote:
>
> > When simulating my back annoted design with modelsim, I get unexpected
> > behavior when using a simulation step of 1ns, but no errors when using
> > a step of 1ps.
>
> > My design is running at 1MHz (so I expect a simulation step of 1ns to
> > be highly sufficient).
> > The part that is causing trouble is a wrapper around an SRAM instance
> > (it is an actel RAM512x18 component on an actel proasic3 FPGA).
>
> The selected technology knows delays below 1 ns, your clock frequency
> is not everything to take into account.
> Consider you have in clock tree between two register 2 buffer
> difference with 100 ps delay each leading to a skew of 200 ps between
> those registers and in datapath 1 cell with 500 ps delay.
> Using 1ns resolution would lead to 2 ns skew vs 1 ns data which ends
> up with 1 ns data before clock violation against 300 ps clock before
> data when using 1 ps resolution.
>
> regards Thomas

Thanks I will use 1ps resolution then.
I still find weird that modelsim (or VITAL libraries) does not warn in
such cases.

Regards

On Jun 20, 8:52=A0am, JB <jb.dubois....@gmail.com> wrote:

>
> Thanks I will use 1ps resolution then.
> I still find weird that modelsim (or VITAL libraries) does not warn in
> such cases.
>

Recheck the transcript right at the start before running for the
following type of message:

The minimum time resolution limit (1ps) in the Verilog source is
smaller than the one chosen for SystemC or VHDL units in the design.
Use the vsim -t option to specify the desired resolution.

KJ

On Jun 20, 6:12=A0am, JB <jb.dubois....@gmail.com> wrote:
> Hello all,
>
> I struggle with an issue I can't understand the root cause.
>
> When simulating my back annoted design with modelsim, I get unexpected
> behavior when using a simulation step of 1ns, but no errors when using
> a step of 1ps.
>
> My design is running at 1MHz (so I expect a simulation step of 1ns to
> be highly sufficient).
> The part that is causing trouble is a wrapper around an SRAM instance
> (it is an actel RAM512x18 component on an actel proasic3 FPGA).
>
> I've got the exact same component instanciated in the exact same
> wrapper simulating fine on an actel igloo FPGA. I am aware that place
> and route may have produce significantly different results between the
> two FPGAs and that having the design running smoothly on one FPGA
> don't prove anything.
>
> Still I can't figure out why modelsim would not simulate identically
> using a 1ns or 1ps step.
>
> Last but not least, I've got no warning from modelsim (no glitch
> found).
>
> If any of you have an idea of what could be happening there I would be
> glad to ear it.
>
> Regards

I don't see evidence that this is your problem, but a classic "back-
annotated sim time resolution problem" that often arises is the mixing
of your testbench environment made up only of idealistic delays (i.e.
delays are only based on the temporal ordering assignments made by
your simulator) with your back-annotated "real world" worst case
delays. For instance, if you attempt to clock a signal from a simple
clocked assignment statement into a back-annotated reg with a real
setup time assigned to it, it will always be one cycle behind. A
typical fix for this is to add an artificial delay to your testbench
assignment statements that interact directly with the back-annotated
code to satisfy the setup times.
- John

On Jun 21, 4:04=A0pm, jc <jcappe...@optimal-design.com> wrote:
> On Jun 20, 6:12=A0am, JB <jb.dubois....@gmail.com> wrote:
>
>
>
>
>
>
>
>
>
> > Hello all,
>
> > I struggle with an issue I can't understand the root cause.
>
> > When simulating my back annoted design with modelsim, I get unexpected
> > behavior when using a simulation step of 1ns, but no errors when using
> > a step of 1ps.
>
> > My design is running at 1MHz (so I expect a simulation step of 1ns to
> > be highly sufficient).
> > The part that is causing trouble is a wrapper around an SRAM instance
> > (it is an actel RAM512x18 component on an actel proasic3 FPGA).
>
> > I've got the exact same component instanciated in the exact same
> > wrapper simulating fine on an actel igloo FPGA. I am aware that place
> > and route may have produce significantly different results between the
> > two FPGAs and that having the design running smoothly on one FPGA
> > don't prove anything.
>
> > Still I can't figure out why modelsim would not simulate identically
> > using a 1ns or 1ps step.
>
> > Last but not least, I've got no warning from modelsim (no glitch
> > found).
>
> > If any of you have an idea of what could be happening there I would be
> > glad to ear it.
>
> > Regards
>
> I don't see evidence that this is your problem, but a classic "back-
> annotated sim time resolution problem" that often arises is the mixing
> of your testbench environment made up only of idealistic delays (i.e.
> delays are only based on the temporal ordering assignments made by
> your simulator) with your back-annotated "real world" worst case
> delays. For instance, if you attempt to clock a signal from a simple
> clocked assignment statement into a back-annotated reg with a real
> setup time assigned to it, it will always be one cycle behind. A
> typical fix for this is to add an artificial delay to your testbench
> assignment statements that interact directly with the back-annotated
> code to satisfy the setup times.
> - John

should probably use correct timescale directives.

Thanks
Shyam

On 20 juin, 18:23, KJ <kkjenni...@sbcglobal.net> wrote:
> On Jun 20, 8:52=A0am, JB <jb.dubois....@gmail.com> wrote:
>
>
>
> > Thanks I will use 1ps resolution then.
> > I still find weird that modelsim (or VITAL libraries) does not warn in
> > such cases.
>
> Recheck the transcript right at the start before running for the
> following type of message:
>
> The minimum time resolution limit (1ps) in the Verilog source is
> smaller than the one chosen for SystemC or VHDL units in the design.
> Use the vsim -t option to specify the desired resolution.
>
> KJ

Well, I re-checked and there is no such warning in the transcript....
Maybe modesim does not warn if a timing is extracted from an SDF back
annotation and not "hard coded" into the libraries, which I guess is
the case here.

On 21 juin, 13:04, jc <jcappe...@optimal-design.com> wrote:
> On Jun 20, 6:12=A0am, JB <jb.dubois....@gmail.com> wrote:
>
>
>
>
>
>
>
>
>
> > Hello all,
>
> > I struggle with an issue I can't understand the root cause.
>
> > When simulating my back annoted design with modelsim, I get unexpected
> > behavior when using a simulation step of 1ns, but no errors when using
> > a step of 1ps.
>
> > My design is running at 1MHz (so I expect a simulation step of 1ns to
> > be highly sufficient).
> > The part that is causing trouble is a wrapper around an SRAM instance
> > (it is an actel RAM512x18 component on an actel proasic3 FPGA).
>
> > I've got the exact same component instanciated in the exact same
> > wrapper simulating fine on an actel igloo FPGA. I am aware that place
> > and route may have produce significantly different results between the
> > two FPGAs and that having the design running smoothly on one FPGA
> > don't prove anything.
>
> > Still I can't figure out why modelsim would not simulate identically
> > using a 1ns or 1ps step.
>
> > Last but not least, I've got no warning from modelsim (no glitch
> > found).
>
> > If any of you have an idea of what could be happening there I would be
> > glad to ear it.
>
> > Regards
>
> I don't see evidence that this is your problem, but a classic "back-
> annotated sim time resolution problem" that often arises is the mixing
> of your testbench environment made up only of idealistic delays (i.e.
> delays are only based on the temporal ordering assignments made by
> your simulator) with your back-annotated "real world" worst case
> delays. For instance, if you attempt to clock a signal from a simple
> clocked assignment statement into a back-annotated reg with a real
> setup time assigned to it, it will always be one cycle behind. A
> typical fix for this is to add an artificial delay to your testbench
> assignment statements that interact directly with the back-annotated
> code to satisfy the setup times.
> - John

I simulate my design as a black box with delays that can be quite
random and never synched with the clock. It may happen that modelsim
detects timing violation on the antimetastability FF inputs but the
design shall be robust to that.

Anyway simulating at 1ps got solved my problem.

I called Actel to ask them what was the optimal time resolution to
gain simulation perfomance without trading accuracy and the only
answer I got is "generate a simulation through Libero and look in the
generated .do file for the requested time resolution", which I did and
it was 1ps.

I find weird that this advised resolution can't not found in any Actel
documentation I've searched, except one application note which request
1ps only if using a PLL (which was not my case).

Thanks anyway for your advices.

On Jun 21, 6:59=A0pm, JB <jb.dubois....@gmail.com> wrote:
> On 20 juin, 18:23, KJ <kkjenni...@sbcglobal.net> wrote:
>
>
>
>
>
> > On Jun 20, 8:52=A0am, JB <jb.dubois....@gmail.com> wrote:
>
> > > Thanks I will use 1ps resolution then.
> > > I still find weird that modelsim (or VITAL libraries) does not warn i=
n
> > > such cases.
>
> > Recheck the transcript right at the start before running for the
> > following type of message:
>
> > The minimum time resolution limit (1ps) in the Verilog source is
> > smaller than the one chosen for SystemC or VHDL units in the design.
> > Use the vsim -t option to specify the desired resolution.
>
> > KJ
>
> Well, I re-checked and there is no such warning in the transcript....
> Maybe modesim does not warn if a timing is extracted from an SDF back
> annotation and not "hard coded" into the libraries, which I guess is
> the case here.- Hide quoted text -
>

Do you have all messages enabled?  Under simulation run-time options
there are choices to disable certain levels of messages ('note',
'warning', 'error').

KJ

On 22 juin, 01:38, KJ <kkjenni...@sbcglobal.net> wrote:
> On Jun 21, 6:59=A0pm, JB <jb.dubois....@gmail.com> wrote:
>
>
>
>
>
>
>
>
>
> > On 20 juin, 18:23, KJ <kkjenni...@sbcglobal.net> wrote:
>
> > > On Jun 20, 8:52=A0am, JB <jb.dubois....@gmail.com> wrote:
>
> > > > Thanks I will use 1ps resolution then.
> > > > I still find weird that modelsim (or VITAL libraries) does not warn=
 in
> > > > such cases.
>
> > > Recheck the transcript right at the start before running for the
> > > following type of message:
>
> > > The minimum time resolution limit (1ps) in the Verilog source is
> > > smaller than the one chosen for SystemC or VHDL units in the design.
> > > Use the vsim -t option to specify the desired resolution.
>
> > > KJ
>
> > Well, I re-checked and there is no such warning in the transcript....
> > Maybe modesim does not warn if a timing is extracted from an SDF back
> > annotation and not "hard coded" into the libraries, which I guess is
> > the case here.- Hide quoted text -
>
> Do you have all messages enabled? =A0Under simulation run-time options
> there are choices to disable certain levels of messages ('note',
> 'warning', 'error').
>
> KJ

I launch the simulation using a command line, the only disabled
message are VITAL glitch messages (+no_glitch_msg). From what I've
read (mostly) all messages are enabled by default.