On Jul 19, 3:20=A0am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:> On Jul 18, 8:32=A0am, "salimbaba" > > <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: > > >Which signal is being mapped on to the INIT_B pad? =A0And where did yo=u> > >constrain this signal to be LOC'ed to? > > > >You are using LOC constraints on all of your I/O right? > > > >Ed McGettigan > > >-- > > >Xilinx Inc. > > > It is an IO which i didnt LOC'ed so INIT_B was mapped on to it.And i am=not> > using LOC constraints on all the IOs .. =A0 =A0 > > > --------------------------------------- =A0 =A0 =A0 =A0 > > Posted throughhttp://www.FPGARelated.com > > Creating a design to be downloaded into a board without fully LOC > constraining all of the IO is just asking for trouble and can > potentially damage the FPGA or another device on the board. > > You need to fix this ASAP and it will very likely resolve your > original problem. > > Ed McGettigan > -- > Xilinx Inc.Ed's point is very much valid. You should fully Constrain all the IO signals in your design before you start implementation. I have faced this problem long back. Every board has specific pins for JTAG interface, but if you don't constrain your IOBs, it may end up in using these JTAG specific IO's by your normal logic IO signals. -- vasu
FPGA not getting programmed
Started by ●July 14, 2011
Reply by ●July 19, 20112011-07-19
Reply by ●July 19, 20112011-07-19
On Jul 19, 12:54=A0am, vasu <vasu.devun...@gmail.com> wrote:> On Jul 19, 3:20=A0am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > > > > > > On Jul 18, 8:32=A0am, "salimbaba" > > > <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: > > > >Which signal is being mapped on to the INIT_B pad? =A0And where did =you> > > >constrain this signal to be LOC'ed to? > > > > >You are using LOC constraints on all of your I/O right? > > > > >Ed McGettigan > > > >-- > > > >Xilinx Inc. > > > > It is an IO which i didnt LOC'ed so INIT_B was mapped on to it.And i =am not> > > using LOC constraints on all the IOs .. =A0 =A0 > > > > --------------------------------------- =A0 =A0 =A0 =A0 > > > Posted throughhttp://www.FPGARelated.com > > > Creating a design to be downloaded into a board without fully LOC > > constraining all of the IO is just asking for trouble and can > > potentially damage the FPGA or another device on the board. > > > You need to fix this ASAP and it will very likely resolve your > > original problem. > > > Ed McGettigan > > -- > > Xilinx Inc. > > Ed's point is very much valid. You should fully Constrain all the IO > signals in your design =A0before you start implementation. I have faced > this problem long back. Every board has specific pins for JTAG > interface, but if you don't constrain your IOBs, it may end up in > using these JTAG specific IO's by your normal logic IO signals. > > -- vasu- Hide quoted text - > > - Show quoted text -Some older FPGA families did not use dedicated JTAG pins, but all modern FPGAs do have dedicated JTAG pins. Ed McGettigan -- Xilinx Inc.
Reply by ●July 20, 20112011-07-20
On Jul 20, 5:19=A0am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:> On Jul 19, 12:54=A0am, vasu <vasu.devun...@gmail.com> wrote: > > > > > > > > > > > On Jul 19, 3:20=A0am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > > > On Jul 18, 8:32=A0am, "salimbaba" > > > > <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: > > > > >Which signal is being mapped on to the INIT_B pad? =A0And where di=d you> > > > >constrain this signal to be LOC'ed to? > > > > > >You are using LOC constraints on all of your I/O right? > > > > > >Ed McGettigan > > > > >-- > > > > >Xilinx Inc. > > > > > It is an IO which i didnt LOC'ed so INIT_B was mapped on to it.And =i am not> > > > using LOC constraints on all the IOs .. =A0 =A0 > > > > > --------------------------------------- =A0 =A0 =A0 =A0 > > > > Posted throughhttp://www.FPGARelated.com > > > > Creating a design to be downloaded into a board without fully LOC > > > constraining all of the IO is just asking for trouble and can > > > potentially damage the FPGA or another device on the board. > > > > You need to fix this ASAP and it will very likely resolve your > > > original problem. > > > > Ed McGettigan > > > -- > > > Xilinx Inc. > > > Ed's point is very much valid. You should fully Constrain all the IO > > signals in your design =A0before you start implementation. I have faced > > this problem long back. Every board has specific pins for JTAG > > interface, but if you don't constrain your IOBs, it may end up in > > using these JTAG specific IO's by your normal logic IO signals. > > > -- vasu- Hide quoted text - > > > - Show quoted text - > > Some older FPGA families did not use dedicated JTAG pins, but all > modern FPGAs do have dedicated JTAG pins. > > Ed McGettigan > -- > Xilinx Inc.I faced this problem in Virtex-6 FPGA based design.
Reply by ●July 20, 20112011-07-20
"Ed McGettigan" <ed.mcgettigan@xilinx.com> wrote in message news:1b9eb6a7-70d2-44fa-9710-0c2eb22262db@t8g2000prm.googlegroups.com...>Some older FPGA families did not use dedicated JTAG pins, but all >modern FPGAs do have dedicated JTAG pins.I guess modern FPGA's have just sw dedicated jtag pins.. At least Altera's can be used as IO through megafunctions (like sld_virtual_jtag). I agree that's the way to do it instead of letting them loose as generic io.
Reply by ●July 21, 20112011-07-21
I am wondering if have two FPGAs being programmed from the same EEPROM is even a valid JTAG structure? Someone please correct if I am incorrect and has designed a working system this way before. I would almost lean towards having the JTAG chain only be EEPROM -> FPGA1 Then have FPGA1 read the bit stream out of EEPROM and program FPGA2. Therefore you don't have bus contention between the two FPGAs. FPGA2 is then like a ghost FPGA on the JTAG chain. Does this seem logical? I have just never heard of one EEPROM being dedicated to two FPGAs before with identical bit files.
Reply by ●July 21, 20112011-07-21
Dustin Brothers wrote:> I am wondering if have two FPGAs being programmed from the same EEPROM is even a valid JTAG structure? Someone please correct if I am incorrect and has designed a working system this way before. I would almost lean towards having the JTAG chain only be > > EEPROM -> FPGA1 > > Then have FPGA1 read the bit stream out of EEPROM and program FPGA2. Therefore you don't have bus contention between the two FPGAs. FPGA2 is then like a ghost FPGA on the JTAG chain. > > Does this seem logical? I have just never heard of one EEPROM being dedicated to two FPGAs before with identical bit files.Actually it is quite common to use a single PROM or flash to program multiple FPGA's. This connection scheme is shown in the Spartan 3 Generation Configuration User Guide. From the other posts in the thread, it seems more likely to be a problem with bit file generation rather than the board-level connections. -- Gabor
Reply by ●July 25, 20112011-07-25
