What can I do if my chip can't meet timing?

Hi, there:

My clock is 40MHz, but I have complicated FFT operations and other DSP
stuff.
The longest path is 25.8ns, though after I set the constraints at
23ns...Previously it
was 27.5ns at constraints of 25ns...

What may I do now? How far can over constraining go? The source codes are
from
other people so I can't change a lot of it.

Besides -opt_mode Speed in XST, what else controls can I use in ISE6.1?

Does Synplify optimize for speed? How does it compare with XST?

Kelvin

"Student" <student@nowhere.com> wrote in message news:<40b2f02e@news.starhub.net.sg>...
> Hi, there:
> 
> My clock is 40MHz, but I have complicated FFT operations and other DSP
> stuff.
> The longest path is 25.8ns, though after I set the constraints at
> 23ns...Previously it
> was 27.5ns at constraints of 25ns...
> 
> What may I do now? How far can over constraining go? The source codes are
> from
> other people so I can't change a lot of it.
> 
> Besides -opt_mode Speed in XST, what else controls can I use in ISE6.1?
> 
> Does Synplify optimize for speed? How does it compare with XST?
> 
> Kelvin

Hi Kelvin,

if the source codes are from other people and you cannot change it
you should assume that is has been optimized for 40MHz, isn't it?  ;o)

You have to clarify for which clock frequency the original design has
been developed.

So basically the best possibility is to think about pipelining your design.
By doing so you will not have to worry about constraining.

Rgds

> My clock is 40MHz, but I have complicated FFT operations and other DSP
> stuff.
> The longest path is 25.8ns, though after I set the constraints at
> 23ns...Previously it
> was 27.5ns at constraints of 25ns...
> 
> What may I do now? How far can over constraining go? 

Keep going until the results don't get any better.

> The source codes are
> from
> other people so I can't change a lot of it.
> 
> Besides -opt_mode Speed in XST, what else controls can I use in ISE6.1?

I think there is -opt_level (or something) that makes it work harder.

Also, you can set the P&R optimisation level.

Note: Estimated frequency after synthesis is not necessarily what you
will get after P&R.

> 
> Does Synplify optimize for speed? 

Yes.

> How does it compare with XST?

I have found it to be better. The extra performance is often very
heavily design dependant. More often than not, for me, it performs
much better with large designs.

Cheers,
JonB

You may want to try to run map with the '-timing' option.

For more ideas check out this Tech Tip from Xilinx:
http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sGlobalNavPick=&sSecondaryNavPick=&category=&iLanguageID=1&multPartNum=1&sTechX_ID=rw_tim_closure

Shalin-

Jon Beniston wrote:
>>My clock is 40MHz, but I have complicated FFT operations and other DSP
>>stuff.
>>The longest path is 25.8ns, though after I set the constraints at
>>23ns...Previously it
>>was 27.5ns at constraints of 25ns...
>>
>>What may I do now? How far can over constraining go? 
> 
> 
> Keep going until the results don't get any better.
> 
> 
>>The source codes are
>>from
>>other people so I can't change a lot of it.
>>
>>Besides -opt_mode Speed in XST, what else controls can I use in ISE6.1?
> 
> 
> I think there is -opt_level (or something) that makes it work harder.
> 
> Also, you can set the P&R optimisation level.
> 
> Note: Estimated frequency after synthesis is not necessarily what you
> will get after P&R.
> 
> 
>>Does Synplify optimize for speed? 
> 
> 
> Yes.
> 
> 
>>How does it compare with XST?
> 
> 
> I have found it to be better. The extra performance is often very
> heavily design dependant. More often than not, for me, it performs
> much better with large designs.
> 
> Cheers,
> JonB

Hi,
As you're pretty close to meeting the timing, your best bet may be to read
up about the Floorplanner. You just(!) need to place your critical logic.
Also, you may be able to persuade Synplify to work better, this has worked
for me in the past, especially if the design is pipelined.
Be careful with over-contraining, it can often make things worse. Read the
CAF archive to find out why. Mr. Andraka gripes about this a fair bit! ;-)
Other less practicable alternatives include freezing, using a faster
speedgrade, and turning up the supply voltage a bit! The Xilinx tools let
you specify the temperature and supply voltage, check out Speedprint.
HTH, Syms.

Here are some hardware ideas to boost performance a few percent:
Buy a higher speed-grade part (usually improves performance by 15% per
speed grade)
Kep the internal supply voltage at or slightly above nominal. That gives
you another 5%.
Somehow keep the chip from getting hot...

Peter Alfke
======================

Shalin Sheth wrote:
> 
> You may want to try to run map with the '-timing' option.
> 
> For more ideas check out this Tech Tip from Xilinx:
> http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sGlobalNavPick=&sSecondaryNavPick=&category=&iLanguageID=1&multPartNum=1&sTechX_ID=rw_tim_closure
> 
> Shalin-
> 
> Jon Beniston wrote:
> >>My clock is 40MHz, but I have complicated FFT operations and other DSP
> >>stuff.
> >>The longest path is 25.8ns, though after I set the constraints at
> >>23ns...Previously it
> >>was 27.5ns at constraints of 25ns...
> >>
> >>What may I do now? How far can over constraining go?
> >
> >
> > Keep going until the results don't get any better.
> >
> >
> >>The source codes are
> >>from
> >>other people so I can't change a lot of it.
> >>
> >>Besides -opt_mode Speed in XST, what else controls can I use in ISE6.1?
> >
> >
> > I think there is -opt_level (or something) that makes it work harder.
> >
> > Also, you can set the P&R optimisation level.
> >
> > Note: Estimated frequency after synthesis is not necessarily what you
> > will get after P&R.
> >
> >
> >>Does Synplify optimize for speed?
> >
> >
> > Yes.
> >
> >
> >>How does it compare with XST?
> >
> >
> > I have found it to be better. The extra performance is often very
> > heavily design dependant. More often than not, for me, it performs
> > much better with large designs.
> >
> > Cheers,
> > JonB

Thanks for your advice.

I have no control over chip and board...
The speed is 40MHz and it is fixed too.

Kelvin






"Peter Alfke" <peter@xilinx.com> wrote in message
news:40B3870C.FE839F7E@xilinx.com...
> Here are some hardware ideas to boost performance a few percent:
> Buy a higher speed-grade part (usually improves performance by 15% per
> speed grade)
> Kep the internal supply voltage at or slightly above nominal. That gives
> you another 5%.
> Somehow keep the chip from getting hot...
>
> Peter Alfke
> ======================
>
> Shalin Sheth wrote:
> >
> > You may want to try to run map with the '-timing' option.
> >
> > For more ideas check out this Tech Tip from Xilinx:
> >
http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sGlobalNavPick=&sSecondaryNavPick=&category=&iLanguageID=1&multPartNum=1&sTechX_ID=rw_tim_closure
> >
> > Shalin-
> >
> > Jon Beniston wrote:
> > >>My clock is 40MHz, but I have complicated FFT operations and other DSP
> > >>stuff.
> > >>The longest path is 25.8ns, though after I set the constraints at
> > >>23ns...Previously it
> > >>was 27.5ns at constraints of 25ns...
> > >>
> > >>What may I do now? How far can over constraining go?
> > >
> > >
> > > Keep going until the results don't get any better.
> > >
> > >
> > >>The source codes are
> > >>from
> > >>other people so I can't change a lot of it.
> > >>
> > >>Besides -opt_mode Speed in XST, what else controls can I use in
ISE6.1?
> > >
> > >
> > > I think there is -opt_level (or something) that makes it work harder.
> > >
> > > Also, you can set the P&R optimisation level.
> > >
> > > Note: Estimated frequency after synthesis is not necessarily what you
> > > will get after P&R.
> > >
> > >
> > >>Does Synplify optimize for speed?
> > >
> > >
> > > Yes.
> > >
> > >
> > >>How does it compare with XST?
> > >
> > >
> > > I have found it to be better. The extra performance is often very
> > > heavily design dependant. More often than not, for me, it performs
> > > much better with large designs.
> > >
> > > Cheers,
> > > JonB

Thanks.

The frequency is fixed and RTL is documented to operate at 40MHz.
I will tamper with the tools for a while instead of havocing with the codes.
Codes change will be my last resort...

Kelvin




"ALuPin" <ALuPin@web.de> wrote in message
news:b8a9a7b0.0405250502.385b73b0@posting.google.com...
> "Student" <student@nowhere.com> wrote in message
news:<40b2f02e@news.starhub.net.sg>...
> > Hi, there:
> >
> > My clock is 40MHz, but I have complicated FFT operations and other DSP
> > stuff.
> > The longest path is 25.8ns, though after I set the constraints at
> > 23ns...Previously it
> > was 27.5ns at constraints of 25ns...
> >
> > What may I do now? How far can over constraining go? The source codes
are
> > from
> > other people so I can't change a lot of it.
> >
> > Besides -opt_mode Speed in XST, what else controls can I use in ISE6.1?
> >
> > Does Synplify optimize for speed? How does it compare with XST?
> >
> > Kelvin
>
> Hi Kelvin,
>
> if the source codes are from other people and you cannot change it
> you should assume that is has been optimized for 40MHz, isn't it?  ;o)
>
> You have to clarify for which clock frequency the original design has
> been developed.
>
> So basically the best possibility is to think about pipelining your
design.
> By doing so you will not have to worry about constraining.
>
> Rgds

You can try multi-pass place and route as well.

-- 
RobertP.

On Tue, 25 May 2004 15:12:45 +0800, Student wrote:

> Hi, there:
> 
> My clock is 40MHz, but I have complicated FFT operations and other DSP
> stuff.
> The longest path is 25.8ns, though after I set the constraints at
> 23ns...Previously it
> was 27.5ns at constraints of 25ns...
> 
> What may I do now? How far can over constraining go? The source codes are
> from
> other people so I can't change a lot of it.
> 
> Besides -opt_mode Speed in XST, what else controls can I use in ISE6.1?
> 
> Does Synplify optimize for speed? How does it compare with XST?
> 
> Kelvin

Synplify usually does a 10% better job then any other synthesis tool so it
might fix your problem. You could also try ISE6.2sp2. XST is an immature
tool so three are significant improvements with each release at this
stage. The final thing to try is floorplanning.