VHDL Basic Question

I am new to VHDL and need some advice on connecting a vector array on an
entity using a port map.I have an array of std_logic_vectors(63 downto 0)
as a port. There are 3 of these in the array. How do I connect these 3
vectors using a port map?

TIA

Jon
	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

On Sat, 20 Aug 2011 09:47:16 -0500, "maxascent"
<maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> wrote:

>I am new to VHDL and need some advice on connecting a vector array on an
>entity using a port map.I have an array of std_logic_vectors(63 downto 0)
>as a port. There are 3 of these in the array. How do I connect these 3
>vectors using a port map?

So it's something like this:

  library ieee;
  use ieee.std_logic_1164.all;
  package vec_array_pkg is
     type a_3x64 is array(0 to 2) of std_logic_vector(63 downto 0);
  end package;

  library ieee;
  use ieee.std_logic_1164.all;
  use work.vec_array_pkg.all;
  entity has_array_port is
    port ( p: in a_3x64; ...

If your external signal is also an array of three 64-bit SLVs, then
simply connect the external array signal to the port.  They have
the same type, and so can be connected.

If your external signal is really three separate 64-bit
signals, then proceed like this:

  signal P,Q,R: std_logic_vector(63 downto 0);
  ...
  my_instance: entity work.has_array_port
        port map ( p(0) => P, p(1) => Q, p(2) => R, ...

-- 
Jonathan Bromley

>On Sat, 20 Aug 2011 09:47:16 -0500, "maxascent"
><maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> wrote:
>
>>I am new to VHDL and need some advice on connecting a vector array on an
>>entity using a port map.I have an array of std_logic_vectors(63 downto
0)
>>as a port. There are 3 of these in the array. How do I connect these 3
>>vectors using a port map?
>
>So it's something like this:
>
>  library ieee;
>  use ieee.std_logic_1164.all;
>  package vec_array_pkg is
>     type a_3x64 is array(0 to 2) of std_logic_vector(63 downto 0);
>  end package;
>
>  library ieee;
>  use ieee.std_logic_1164.all;
>  use work.vec_array_pkg.all;
>  entity has_array_port is
>    port ( p: in a_3x64; ...
>
>If your external signal is also an array of three 64-bit SLVs, then
>simply connect the external array signal to the port.  They have
>the same type, and so can be connected.
>
>If your external signal is really three separate 64-bit
>signals, then proceed like this:
>
>  signal P,Q,R: std_logic_vector(63 downto 0);
>  ...
>  my_instance: entity work.has_array_port
>        port map ( p(0) => P, p(1) => Q, p(2) => R, ...
>
>-- 
>Jonathan Bromley
>

I really want the type to be something like this

constant M : positive := 64;
type a_nxm is array(natural range <>) of std_logic_vector(M-1 downto 0);

and then

entity has_array_port is
generic(
 IP_NUM     : integer := 3;
);
  port ( p: in a_nxm(0 to IP_NUM-1) 

Not sure if I have written this correctly? What I am trying to do is create
a generic mux. So for example, I may want 3, 64 bit slv.

Thanks

Jon	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

On Sat, 20 Aug 2011 10:24:33 -0500, "maxascent" wrote:

>I really want the type to be something like this
>
>constant M : positive := 64;
>type a_nxm is array(natural range <>) of std_logic_vector(M-1 downto 0);
>
>and then
>
>entity has_array_port is
>generic(
> IP_NUM     : integer := 3;
>);
>  port ( p: in a_nxm(0 to IP_NUM-1) 
>
>Not sure if I have written this correctly?

Looks good.

> What I am trying to do is create
>a generic mux. So for example, I may want 3, 64 bit slv.

This is still fine.  At the point where you instance 
the mux, you know exactly what you plan to connect
to it:

   signal P, Q, R, S: std_logic_vector(M-1 downto 0);
   ...
   my_4way_mux: entity work.has_array_port
      generic_map(IP_NUM => 4)
      port map (p(0) => P, ..., p(3) => S, ...

The problems will start if you want THIS higher level
entity also to be configurable, because then it makes 
no sense whatever to list out the port elements one
by one - such a list would be broken for any different
number of inputs than you wrote it for.  So you'll need
an array signal up there in that top module too.  But
that's fine:

   constant SIZE: integer := 6;
   signal A: array(0 to SIZE-1) of std_logic_vector(M-1 downto 0);
   ...
   my_Nway_mux: entity work.has_array_port
      generic_map(IP_NUM => SIZE)
      port map (p => A, ...

Now, of course, you have the exquisite problem of
how to attach your miscellany of 64-bit signals
to the elements of A... but hey, things have to
get specific somewhere, don't they?  This is a 
typical problem with things like data readback 
muxes for a register file - the mux can be generic,
but the individual registers are all different and
it's hard to parameterize their existence.

Sometimes you can partially solve this by using
an enum type as the array index.  The enum names
then denote individual registers.  It doesn't
solve the problem entirely, but it can make your
eventual solution look less ugly.
-- 
Jonathan Bromley

>On Sat, 20 Aug 2011 10:24:33 -0500, "maxascent" wrote:
>
>>I really want the type to be something like this
>>
>>constant M : positive := 64;
>>type a_nxm is array(natural range <>) of std_logic_vector(M-1 downto 0);
>>
>>and then
>>
>>entity has_array_port is
>>generic(
>> IP_NUM     : integer := 3;
>>);
>>  port ( p: in a_nxm(0 to IP_NUM-1) 
>>
>>Not sure if I have written this correctly?
>
>Looks good.
>
>> What I am trying to do is create
>>a generic mux. So for example, I may want 3, 64 bit slv.
>
>This is still fine.  At the point where you instance 
>the mux, you know exactly what you plan to connect
>to it:
>
>   signal P, Q, R, S: std_logic_vector(M-1 downto 0);
>   ...
>   my_4way_mux: entity work.has_array_port
>      generic_map(IP_NUM => 4)
>      port map (p(0) => P, ..., p(3) => S, ...
>
>The problems will start if you want THIS higher level
>entity also to be configurable, because then it makes 
>no sense whatever to list out the port elements one
>by one - such a list would be broken for any different
>number of inputs than you wrote it for.  So you'll need
>an array signal up there in that top module too.  But
>that's fine:
>
>   constant SIZE: integer := 6;
>   signal A: array(0 to SIZE-1) of std_logic_vector(M-1 downto 0);
>   ...
>   my_Nway_mux: entity work.has_array_port
>      generic_map(IP_NUM => SIZE)
>      port map (p => A, ...
>
>Now, of course, you have the exquisite problem of
>how to attach your miscellany of 64-bit signals
>to the elements of A... but hey, things have to
>get specific somewhere, don't they?  This is a 
>typical problem with things like data readback 
>muxes for a register file - the mux can be generic,
>but the individual registers are all different and
>it's hard to parameterize their existence.
>
>Sometimes you can partially solve this by using
>an enum type as the array index.  The enum names
>then denote individual registers.  It doesn't
>solve the problem entirely, but it can make your
>eventual solution look less ugly.
>-- 
>Jonathan Bromley
>	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

>On Sat, 20 Aug 2011 10:24:33 -0500, "maxascent" wrote:
>
>>I really want the type to be something like this
>>
>>constant M : positive := 64;
>>type a_nxm is array(natural range <>) of std_logic_vector(M-1 downto 0);
>>
>>and then
>>
>>entity has_array_port is
>>generic(
>> IP_NUM     : integer := 3;
>>);
>>  port ( p: in a_nxm(0 to IP_NUM-1) 
>>
>>Not sure if I have written this correctly?
>
>Looks good.
>
>> What I am trying to do is create
>>a generic mux. So for example, I may want 3, 64 bit slv.
>
>This is still fine.  At the point where you instance 
>the mux, you know exactly what you plan to connect
>to it:
>
>   signal P, Q, R, S: std_logic_vector(M-1 downto 0);
>   ...
>   my_4way_mux: entity work.has_array_port
>      generic_map(IP_NUM => 4)
>      port map (p(0) => P, ..., p(3) => S, ...
>
>The problems will start if you want THIS higher level
>entity also to be configurable, because then it makes 
>no sense whatever to list out the port elements one
>by one - such a list would be broken for any different
>number of inputs than you wrote it for.  So you'll need
>an array signal up there in that top module too.  But
>that's fine:
>
>   constant SIZE: integer := 6;
>   signal A: array(0 to SIZE-1) of std_logic_vector(M-1 downto 0);
>   ...
>   my_Nway_mux: entity work.has_array_port
>      generic_map(IP_NUM => SIZE)
>      port map (p => A, ...
>
>Now, of course, you have the exquisite problem of
>how to attach your miscellany of 64-bit signals
>to the elements of A... but hey, things have to
>get specific somewhere, don't they?  This is a 
>typical problem with things like data readback 
>muxes for a register file - the mux can be generic,
>but the individual registers are all different and
>it's hard to parameterize their existence.
>
>Sometimes you can partially solve this by using
>an enum type as the array index.  The enum names
>then denote individual registers.  It doesn't
>solve the problem entirely, but it can make your
>eventual solution look less ugly.
>-- 
>Jonathan Bromley
>

Ok so I have done the above and have and instantiate the mux with 3, 64-bit
inputs. I try and connect a 64-bit vector to one of the inputs and when I
try and simulate I get the following error.

Signal "app_rd_data_i" is type ieee.std_logic_1164.std_logic_vector;
expecting type ieee.std_logic_1164.std_logic.

The signal "app_rd_data_i" is a 64-bit slv and I try and connect it to one
of the mux inputs. Not quite sure why it thinks the mux input is
std_logic?

TIA

Jon	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

On Sat, 20 Aug 2011 14:10:54 -0500, "maxascent" wrote:

>Ok so I have done the above and have and instantiate the mux with 3, 64-bit
>inputs. I try and connect a 64-bit vector to one of the inputs and when I
>try and simulate I get the following error.
>
>Signal "app_rd_data_i" is type ieee.std_logic_1164.std_logic_vector;
>expecting type ieee.std_logic_1164.std_logic.
>
>The signal "app_rd_data_i" is a 64-bit slv and I try and connect it to one
>of the mux inputs. Not quite sure why it thinks the mux input is
>std_logic?

Sounds as though you have put a std_logic_vector port on 
your mux entity, rather than an array port.  The basic
idea is perfectly sound; something must be messed up 
somewhere.
-- 
Jonathan Bromley

>Sounds as though you have put a std_logic_vector port on 
>your mux entity, rather than an array port.  The basic
>idea is perfectly sound; something must be messed up 
>somewhere.
>-- 
>Jonathan Bromley
>

I fixed the problem; I had left an old component declaration in the
package. I just have one final question. If I have the following type in a
package :-

constant MUX_DATA_BITS : integer := 64;
constant MUX_IP_NUM    : integer := 8;
type mux_array is array(0 to MUX_IP_NUM-1) of
std_logic_vector(MUX_DATA_BITS-1 downto 0);

How do I override the two constants when I instantiate my mux so that I can
have different input vectors and input numbers?

Thanks

Jon	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

"maxascent" <maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> wrote:

>
>>Sounds as though you have put a std_logic_vector port on 
>>your mux entity, rather than an array port.  The basic
>>idea is perfectly sound; something must be messed up 
>>somewhere.
>>-- 
>>Jonathan Bromley
>>
>
>I fixed the problem; I had left an old component declaration in the
>package. I just have one final question. If I have the following type in a
>package :-
>
>constant MUX_DATA_BITS : integer := 64;
>constant MUX_IP_NUM    : integer := 8;
>type mux_array is array(0 to MUX_IP_NUM-1) of
>std_logic_vector(MUX_DATA_BITS-1 downto 0);
>
>How do I override the two constants when I instantiate my mux so that I can
>have different input vectors and input numbers?

These sort of 'problems' are best solved by creating a function.

-- 
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico@nctdevpuntnl (punt=.)
--------------------------------------------------------------

I am trying to create a generic mux that I can just instantiate in any
design. I have done this in Verilog quite easily, but it seems VHDL is a
different matter.

Jon	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com