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cheating Arria FPGA i/o count

Started by John Larkin August 27, 2011
Hi,

I'm designing a pretty horrible board (33 page schematic!) that will
use an Altera Arria II GX in the 572BGA package. There are 240 pure
I/O pins in this package, and 12 dedicated clock pins. I'm getting
close to using up all the i/o pins, and starting to do silly things to
save a pin here and there. Don't blame me, blame customer feature
creep!

So, is it possible to use clock pins as general-purpose inputs? The
documentation doesn't say so, but it does imply somewhere that clock
nets can be used for non-clock functions like async resets, so there
should be some not-too-disgusting way to used them as slow static
inputs.

Pity they didn't dual-purpose the clock pins. It's not often you need
12 clocks.

Any thoughts/experience here?

Thanks

John


On 28 Aug., 00:58, John Larkin
<jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
> Hi, > > I'm designing a pretty horrible board (33 page schematic!) that will > use an Altera Arria II GX in the 572BGA package. There are 240 pure > I/O pins in this package, and 12 dedicated clock pins. I'm getting > close to using up all the i/o pins, and starting to do silly things to > save a pin here and there. Don't blame me, blame customer feature > creep! > > So, is it possible to use clock pins as general-purpose inputs? The > documentation doesn't say so, but it does imply somewhere that clock > nets can be used for non-clock functions like async resets, so there > should be some not-too-disgusting way to used them as slow static > inputs. > > Pity they didn't dual-purpose the clock pins. It's not often you need > 12 clocks. > > Any thoughts/experience here? > > Thanks > > John
never used altera, but I'd think it is in here somewhere: www.altera.com/download/board-layout-test/schematic-review-ws/worksheets/Arria_GX_Schematic_Review_Worksheet.doc -Lasse

"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in 
message news:3jsi579k5mhhectd2ej80jhme53h348ib5@4ax.com...
> Hi, > > I'm designing a pretty horrible board (33 page schematic!) that will > use an Altera Arria II GX in the 572BGA package. There are 240 pure > I/O pins in this package, and 12 dedicated clock pins. I'm getting > close to using up all the i/o pins, and starting to do silly things to > save a pin here and there. Don't blame me, blame customer feature > creep! > > So, is it possible to use clock pins as general-purpose inputs? The > documentation doesn't say so, but it does imply somewhere that clock > nets can be used for non-clock functions like async resets, so there > should be some not-too-disgusting way to used them as slow static > inputs. > > Pity they didn't dual-purpose the clock pins. It's not often you need > 12 clocks. > > Any thoughts/experience here? > > Thanks > > John > >
I don&#4294967295;t see why not, dedicated clocks mean that propagation time is minimized across the chip. But Quartus may balk at the idea. see <http://www.altera.com/literature/lit-dpcg.jsp> Some pins could be used as I/O , some can't. Cheers
On Aug 27, 11:58=A0pm, John Larkin
<jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
> Hi, > > I'm designing a pretty horrible board (33 page schematic!) that will > use an Altera Arria II GX in the 572BGA package. There are 240 pure > I/O pins in this package, and 12 dedicated clock pins. I'm getting > close to using up all the i/o pins, and starting to do silly things to > save a pin here and there. Don't blame me, blame customer feature > creep! > > So, is it possible to use clock pins as general-purpose inputs? The > documentation doesn't say so, but it does imply somewhere that clock > nets can be used for non-clock functions like async resets, so there > should be some not-too-disgusting way to used them as slow static > inputs. > > Pity they didn't dual-purpose the clock pins. It's not often you need > 12 clocks. > > Any thoughts/experience here? > > Thanks > > John
Just did a test design using an Arria II GX and assigned an input pin to a dedicated clock input and it compiled OK.
On Aug 28, 12:43=A0am, davew <david.wo...@gmail.com> wrote:
> On Aug 27, 11:58=A0pm, John Larkin > > > > > > <jjlar...@highNOTlandTHIStechnologyPART.com> wrote: > > Hi, > > > I'm designing a pretty horrible board (33 page schematic!) that will > > use an Altera Arria II GX in the 572BGA package. There are 240 pure > > I/O pins in this package, and 12 dedicated clock pins. I'm getting > > close to using up all the i/o pins, and starting to do silly things to > > save a pin here and there. Don't blame me, blame customer feature > > creep! > > > So, is it possible to use clock pins as general-purpose inputs? The > > documentation doesn't say so, but it does imply somewhere that clock > > nets can be used for non-clock functions like async resets, so there > > should be some not-too-disgusting way to used them as slow static > > inputs. > > > Pity they didn't dual-purpose the clock pins. It's not often you need > > 12 clocks. > > > Any thoughts/experience here? > > > Thanks > > > John > > Just did a test design using an Arria II GX and assigned an input pin > to a dedicated clock input and it compiled OK.
If you're not sure, assign the pin and run the I/O Assignment Analysis. This validates all your I/O assignments without having to compile any code.
On Sat, 27 Aug 2011 16:43:03 -0700 (PDT), davew
<david.wooff@gmail.com> wrote:

>On Aug 27, 11:58&#4294967295;pm, John Larkin ><jjlar...@highNOTlandTHIStechnologyPART.com> wrote: >> Hi, >> >> I'm designing a pretty horrible board (33 page schematic!) that will >> use an Altera Arria II GX in the 572BGA package. There are 240 pure >> I/O pins in this package, and 12 dedicated clock pins. I'm getting >> close to using up all the i/o pins, and starting to do silly things to >> save a pin here and there. Don't blame me, blame customer feature >> creep! >> >> So, is it possible to use clock pins as general-purpose inputs? The >> documentation doesn't say so, but it does imply somewhere that clock >> nets can be used for non-clock functions like async resets, so there >> should be some not-too-disgusting way to used them as slow static >> inputs. >> >> Pity they didn't dual-purpose the clock pins. It's not often you need >> 12 clocks. >> >> Any thoughts/experience here? >> >> Thanks >> >> John > >Just did a test design using an Arria II GX and assigned an input pin >to a dedicated clock input and it compiled OK.
Cool! I'll have one of my FPGA guys try it, maybe on a real eval board (I don't drive the FPGA software myself.) This very weekend, I'll assume it works and get on with my life. Thanks John
On Sat, 27 Aug 2011 22:44:14 -0700, Robert Baer <robertbaer@localnet.com>
wrote:

>davew wrote: >> On Aug 27, 11:58 pm, John Larkin >> <jjlar...@highNOTlandTHIStechnologyPART.com> wrote: >>> Hi, >>> >>> I'm designing a pretty horrible board (33 page schematic!) that will >>> use an Altera Arria II GX in the 572BGA package. There are 240 pure >>> I/O pins in this package, and 12 dedicated clock pins. I'm getting >>> close to using up all the i/o pins, and starting to do silly things to >>> save a pin here and there. Don't blame me, blame customer feature >>> creep! >>> >>> So, is it possible to use clock pins as general-purpose inputs? The >>> documentation doesn't say so, but it does imply somewhere that clock >>> nets can be used for non-clock functions like async resets, so there >>> should be some not-too-disgusting way to used them as slow static >>> inputs. >>> >>> Pity they didn't dual-purpose the clock pins. It's not often you need >>> 12 clocks. >>> >>> Any thoughts/experience here? >>> >>> Thanks >>> >>> John >> >> Just did a test design using an Arria II GX and assigned an input pin >> to a dedicated clock input and it compiled OK. > Just because a program compiles does not mean it will work...
It does mean the I/O assignment meets the chip's specs, which is all that was asked.
davew wrote:
> On Aug 27, 11:58 pm, John Larkin > <jjlar...@highNOTlandTHIStechnologyPART.com> wrote: >> Hi, >> >> I'm designing a pretty horrible board (33 page schematic!) that will >> use an Altera Arria II GX in the 572BGA package. There are 240 pure >> I/O pins in this package, and 12 dedicated clock pins. I'm getting >> close to using up all the i/o pins, and starting to do silly things to >> save a pin here and there. Don't blame me, blame customer feature >> creep! >> >> So, is it possible to use clock pins as general-purpose inputs? The >> documentation doesn't say so, but it does imply somewhere that clock >> nets can be used for non-clock functions like async resets, so there >> should be some not-too-disgusting way to used them as slow static >> inputs. >> >> Pity they didn't dual-purpose the clock pins. It's not often you need >> 12 clocks. >> >> Any thoughts/experience here? >> >> Thanks >> >> John > > Just did a test design using an Arria II GX and assigned an input pin > to a dedicated clock input and it compiled OK.
Just because a program compiles does not mean it will work...
"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message 
news:3jsi579k5mhhectd2ej80jhme53h348ib5@4ax.com...
> Hi, > > I'm designing a pretty horrible board (33 page schematic!) that will > use an Altera Arria II GX in the 572BGA package. There are 240 pure > I/O pins in this package, and 12 dedicated clock pins. I'm getting > close to using up all the i/o pins, and starting to do silly things to > save a pin here and there. Don't blame me, blame customer feature > creep! > > So, is it possible to use clock pins as general-purpose inputs? The > documentation doesn't say so, but it does imply somewhere that clock > nets can be used for non-clock functions like async resets, so there > should be some not-too-disgusting way to used them as slow static > inputs. > > Pity they didn't dual-purpose the clock pins. It's not often you need > 12 clocks. > > Any thoughts/experience here? > > Thanks > > John > >
Does PS boot mode save a pin or two ?..
> So, is it possible to use clock pins as general-purpose inputs?
For Altera Cyclone X, you can use clock-inputs as general-purpose inputs with some restrictions, most important: - No internal pullups possible - No fast I/O-register It is not possible to use them as output. I guess, the same applies also for the Arria-parts, but I have not double-checked. Regards, Thomas www.entner-electronics.com