"Robert Baer" <robertbaer@localnet.com> wrote in message news:LdadnbDZuLc6WsTTnZ2dnUVZ_hCdnZ2d@posted.localnet...> Just because a program compiles does not mean it will work...It's not Xilinx, it's Altera.
cheating Arria FPGA i/o count
Started by ●August 27, 2011
Reply by ●August 28, 20112011-08-28
Reply by ●August 28, 20112011-08-28
On 28/08/11 06:58, John Larkin wrote:> Hi, > > I'm designing a pretty horrible board (33 page schematic!) that will > use an Altera Arria II GX in the 572BGA package. There are 240 pure > I/O pins in this package, and 12 dedicated clock pins. I'm getting > close to using up all the i/o pins, and starting to do silly things to > save a pin here and there. Don't blame me, blame customer feature > creep! > > So, is it possible to use clock pins as general-purpose inputs? The > documentation doesn't say so, but it does imply somewhere that clock > nets can be used for non-clock functions like async resets, so there > should be some not-too-disgusting way to used them as slow static > inputs. > > Pity they didn't dual-purpose the clock pins. It's not often you need > 12 clocks. > > Any thoughts/experience here? > > Thanks > > John > >I think the people at comp.arch.fpga might be more experienced at this. Werner
Reply by ●August 28, 20112011-08-28
On Sun, 28 Aug 2011 08:11:22 +0100, "TTman" <pcw1.cad@ntlworld.com> wrote:> >"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message >news:3jsi579k5mhhectd2ej80jhme53h348ib5@4ax.com... >> Hi, >> >> I'm designing a pretty horrible board (33 page schematic!) that will >> use an Altera Arria II GX in the 572BGA package. There are 240 pure >> I/O pins in this package, and 12 dedicated clock pins. I'm getting >> close to using up all the i/o pins, and starting to do silly things to >> save a pin here and there. Don't blame me, blame customer feature >> creep! >> >> So, is it possible to use clock pins as general-purpose inputs? The >> documentation doesn't say so, but it does imply somewhere that clock >> nets can be used for non-clock functions like async resets, so there >> should be some not-too-disgusting way to used them as slow static >> inputs. >> >> Pity they didn't dual-purpose the clock pins. It's not often you need >> 12 clocks. >> >> Any thoughts/experience here? >> >> Thanks >> >> John >> >> >Does PS boot mode save a pin or two ?.. >We're doing that already... a mere 29 million bits! John
Reply by ●August 28, 20112011-08-28
On Sun, 28 Aug 2011 02:32:47 -0700 (PDT), Thomas Entner <thomas.entner99@gmail.com> wrote:> >> So, is it possible to use clock pins as general-purpose inputs? > >For Altera Cyclone X, you can use clock-inputs as general-purpose >inputs with some restrictions, most important: >- No internal pullups possible >- No fast I/O-register > >It is not possible to use them as output. > >I guess, the same applies also for the Arria-parts, but I have not >double-checked. > >Regards, > >Thomas > >www.entner-electronics.comThe Arria GZ parts say specifically that clock pins can be I/Os. It's not clear on the GX if they can be inputs. We're using the A2 45GX. My schematic names signals like SIG3_F for FPGA i/o SIG4_FS serdes SIG5_FD special/dedicated SIG6_FI FPGA input, i/o or (maybe) clock pin and I let The Brat (our layout person) pick whichever FPGA pins that route best. There's an ARM processor with similar rules, SIG5_U etc. John
Reply by ●August 28, 20112011-08-28
On Sun, 28 Aug 2011 18:06:39 +0300, "scrts" <mailsoc@[remove@here]gmail.com> wrote:> >"Robert Baer" <robertbaer@localnet.com> wrote in message >news:LdadnbDZuLc6WsTTnZ2dnUVZ_hCdnZ2d@posted.localnet... >> Just because a program compiles does not mean it will work... > >It's not Xilinx, it's Altera. >Ohhh, that was mean. True, but mean. John
Reply by ●August 28, 20112011-08-28
On Mon, 29 Aug 2011 00:47:56 +0800, Werner <wdahn@netfront.net> wrote:>On 28/08/11 06:58, John Larkin wrote: >> Hi, >> >> I'm designing a pretty horrible board (33 page schematic!) that will >> use an Altera Arria II GX in the 572BGA package. There are 240 pure >> I/O pins in this package, and 12 dedicated clock pins. I'm getting >> close to using up all the i/o pins, and starting to do silly things to >> save a pin here and there. Don't blame me, blame customer feature >> creep! >> >> So, is it possible to use clock pins as general-purpose inputs? The >> documentation doesn't say so, but it does imply somewhere that clock >> nets can be used for non-clock functions like async resets, so there >> should be some not-too-disgusting way to used them as slow static >> inputs. >> >> Pity they didn't dual-purpose the clock pins. It's not often you need >> 12 clocks. >> >> Any thoughts/experience here? >> >> Thanks >> >> John >> >> > >I think the people at comp.arch.fpga might be more experienced at this. > >WernerRight. I did crosspost there. John
Reply by ●August 28, 20112011-08-28
On Sun, 28 Aug 2011 10:10:00 -0700, John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote:>On Sun, 28 Aug 2011 18:06:39 +0300, "scrts" ><mailsoc@[remove@here]gmail.com> wrote: > >> >>"Robert Baer" <robertbaer@localnet.com> wrote in message >>news:LdadnbDZuLc6WsTTnZ2dnUVZ_hCdnZ2d@posted.localnet... >>> Just because a program compiles does not mean it will work... >> >>It's not Xilinx, it's Altera. >> > >Ohhh, that was mean. True, but mean.Even Xilinx will tell you about illegal I/O assignments.
Reply by ●August 28, 20112011-08-28
On Sun, 28 Aug 2011 10:08:19 -0700, John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote:>On Sun, 28 Aug 2011 02:32:47 -0700 (PDT), Thomas Entner ><thomas.entner99@gmail.com> wrote: > >> >>> So, is it possible to use clock pins as general-purpose inputs? >> >>For Altera Cyclone X, you can use clock-inputs as general-purpose >>inputs with some restrictions, most important: >>- No internal pullups possible >>- No fast I/O-register >> >>It is not possible to use them as output. >> >>I guess, the same applies also for the Arria-parts, but I have not >>double-checked. >> >>Regards, >> >>Thomas >> >>www.entner-electronics.com > >The Arria GZ parts say specifically that clock pins can be I/Os. It's >not clear on the GX if they can be inputs. We're using the A2 45GX. > >My schematic names signals like > >SIG3_F for FPGA i/o >SIG4_FS serdes >SIG5_FD special/dedicated >SIG6_FI FPGA input, i/o or (maybe) clock pin > >and I let The Brat (our layout person) pick whichever FPGA pins that >route best. There's an ARM processor with similar rules, SIG5_U etc.Are you using I/O banking? I tend to code such things into the schematic symbol, rather than signal names. Also, be careful if you use external RAM I/O macros. Some of these are picky about I/O assignments.
Reply by ●August 28, 20112011-08-28
On Sun, 28 Aug 2011 12:38:07 -0500, "krw@att.bizzzzzzzzzzzz" <krw@att.bizzzzzzzzzzzz> wrote:>On Sun, 28 Aug 2011 10:08:19 -0700, John Larkin ><jjlarkin@highNOTlandTHIStechnologyPART.com> wrote: > >>On Sun, 28 Aug 2011 02:32:47 -0700 (PDT), Thomas Entner >><thomas.entner99@gmail.com> wrote: >> >>> >>>> So, is it possible to use clock pins as general-purpose inputs? >>> >>>For Altera Cyclone X, you can use clock-inputs as general-purpose >>>inputs with some restrictions, most important: >>>- No internal pullups possible >>>- No fast I/O-register >>> >>>It is not possible to use them as output. >>> >>>I guess, the same applies also for the Arria-parts, but I have not >>>double-checked. >>> >>>Regards, >>> >>>Thomas >>> >>>www.entner-electronics.com >> >>The Arria GZ parts say specifically that clock pins can be I/Os. It's >>not clear on the GX if they can be inputs. We're using the A2 45GX. >> >>My schematic names signals like >> >>SIG3_F for FPGA i/o >>SIG4_FS serdes >>SIG5_FD special/dedicated >>SIG6_FI FPGA input, i/o or (maybe) clock pin >> >>and I let The Brat (our layout person) pick whichever FPGA pins that >>route best. There's an ARM processor with similar rules, SIG5_U etc. > >Are you using I/O banking? I tend to code such things into the schematic >symbol, rather than signal names. Also, be careful if you use external RAM >I/O macros. Some of these are picky about I/O assignments.All the banks are 3.3 volts, and no DRAM, so any i/o pin is as good as any other. The main clock is a mere 125 MHz. The schematic symbol for the FPGA is in fact a bunch of separate blocks, "gates" to PADS: a couple for PCIe, one for each i/o bank, one for core power, one for ground, one for config. Each bank block has its own Vccio pins. We are doing PCI Express, but those pins are hard dedicated, so I can assign off-pages to the specific FPGA pins involved, locking them down, and preplan the routing for those. John
Reply by ●August 28, 20112011-08-28
On Sun, 28 Aug 2011 10:49:03 -0700, John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote:>On Sun, 28 Aug 2011 12:38:07 -0500, "krw@att.bizzzzzzzzzzzz" ><krw@att.bizzzzzzzzzzzz> wrote: > >>On Sun, 28 Aug 2011 10:08:19 -0700, John Larkin >><jjlarkin@highNOTlandTHIStechnologyPART.com> wrote: >> >>>On Sun, 28 Aug 2011 02:32:47 -0700 (PDT), Thomas Entner >>><thomas.entner99@gmail.com> wrote: >>> >>>> >>>>> So, is it possible to use clock pins as general-purpose inputs? >>>> >>>>For Altera Cyclone X, you can use clock-inputs as general-purpose >>>>inputs with some restrictions, most important: >>>>- No internal pullups possible >>>>- No fast I/O-register >>>> >>>>It is not possible to use them as output. >>>> >>>>I guess, the same applies also for the Arria-parts, but I have not >>>>double-checked. >>>> >>>>Regards, >>>> >>>>Thomas >>>> >>>>www.entner-electronics.com >>> >>>The Arria GZ parts say specifically that clock pins can be I/Os. It's >>>not clear on the GX if they can be inputs. We're using the A2 45GX. >>> >>>My schematic names signals like >>> >>>SIG3_F for FPGA i/o >>>SIG4_FS serdes >>>SIG5_FD special/dedicated >>>SIG6_FI FPGA input, i/o or (maybe) clock pin >>> >>>and I let The Brat (our layout person) pick whichever FPGA pins that >>>route best. There's an ARM processor with similar rules, SIG5_U etc. >> >>Are you using I/O banking? I tend to code such things into the schematic >>symbol, rather than signal names. Also, be careful if you use external RAM >>I/O macros. Some of these are picky about I/O assignments. > >All the banks are 3.3 volts, and no DRAM, so any i/o pin is as good as >any other. The main clock is a mere 125 MHz. > >The schematic symbol for the FPGA is in fact a bunch of separate >blocks, "gates" to PADS: a couple for PCIe, one for each i/o bank, one >for core power, one for ground, one for config. Each bank block has >its own Vccio pins.Sure, I do the same, except I'll break things down into functional blocks rather than just along bank boundaries. I never reuse symbols for FPGAs. You can still code the pin-swapping information into the pin names.>We are doing PCI Express, but those pins are hard dedicated, so I can >assign off-pages to the specific FPGA pins involved, locking them >down, and preplan the routing for those.Sure, name them with their function and I/O pin number and mark them as non-swappable. Again, there is no need to identify these pins by their signal names. Doesn't hurt, just adds more mess to the naming convention.
