VHDL : function not recognizing a type defined in package

Started by jmca 2 years ago1 replylatest reply 2 years ago70 views


I am trying to write a function that reads from csv file and formats data to fixed point so it can be used to initialize ROM contents.

The function is contained in a package. The package body looks like:

-- Package Body Section
package body file_io_pkg is 
impure function f_init_rom_fixed 
   ( fname : string ;
     path  : string;   
     fsize : integer; 
     int_size : integer;
     dec_size : integer  ) return t_sfixed_vec is 

variable v_csv_file    : csv_file_reader; 
variable v_read_sfixed : t_s16 ;
variable v_sfixed_vec  : t_sfixed_vec;



      for i in 0 to fsize - 1 loop
         v_read_sfixed  := signed(to_sfixed(v_csv_file.read_real, int_size ,- dec_size);   
         v_sfixed_vec(i):= v_read_sfixed; 
      end loop l_read; 

   return v_sfixed_vec;  

end function ;

end package body file_io_pkg;  

I get the following error when elaborating :

Error : 'csv_file_reader' is not declared (VHDL-1241) : C:/FPGA/test_prj/hdl/file_io_pkg.vhd(54) 

But csv_file_reader is a type defined in csv_file_reader_pk (

This package is compiled is imported at the library section of my package.

library work;
use work.csv_file_reader_pkg.all;

So I can't really see why I am getting this error, any hint?

Thanks in advance

[ - ]
Reply by adouvilleJanuary 8, 2020


The type defined into your package (csv_file_read_pk) is csv_file_reader_type (not csv_file_reader)...