Currently, Im designing a processing element.
This design is synthesis in Xilinx ISE Design Suite 14.7 using Virtex 6 XC6VLX75T-2FF484.
I have problem on the timing analysis.
The is no setup time and hold time reported as shown below.
Could anyone please check for me? I really need to know the datapath delay.
The design files are provide to anyone to try.CompMaxSoFar.v