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timing analysis query

Started by dayana42200 2 years ago32 views

Hello everyone.

Currently, Im designing a processing element.

This design is synthesis in Xilinx ISE Design Suite 14.7 using Virtex 6 XC6VLX75T-2FF484.

I have problem on the timing analysis.

The is no setup time and hold time reported as shown below.

2020-01-11_18-41-56_65392.png

Could anyone please check for me? I really need to know the datapath delay.

The design files are provide to anyone to try.

CompMaxSoFar.v

LookUpTable.v

ProcessingElement.v

Sync_Rst_TWO_Input_Adder.v

timing.ucf