Hello,
I implemented running sum filter In FPGA. Input width(IW) is 8 and the log(based two) of the maximum number of averages(LGMEM) is 14. The output/accumulator bit width(OW)=IW+LGMEM. The 8 bit ADC output is filtered using this filter. The ENOB of ADC output before filtering is 5 bits and 11.75 after filtering. The accumulator bit width is 22 and every bit of accumulator is toggling but still ENOB is 11.75. What could be the reason? Does it mean the filter in inefficient?
Kindly someone help me to understand
Based on your other post and your information here I agree with AlanTipper that you're getting basically the expected improvement from oversampling. You are currently very close to the limit of performance for your oversampling rate and ADC precision. For Input Width IW, sampling frequency FS, and signal bandwidth BW the number of effective bits is:
ENOB = IW + 0.5 * log(0.5 * FS / BW) / log(2) [bits]
ENOB = 8 + 0.5 * log(0.5 * 1.5 MHz / 3 kHz) / log(2) [bits]
ENOB = 8 + 3.98 [bits]
ENOB = 11.98 [bits]
This is the limit for an ideal lowpass filter, so the loss you are getting from using a running sum instead is only 0.25 [bits].
Based on the information given, it's unlikely that changing your filter will be worth the added computation/implementation cost.
If you need more performance, here are the options open to you:
- Use a higher precision ADC
- Further increase the oversampling factor
- Use output noise-shaping through analog feedback (Delta-Sigma Modulation [Wiki and free book on the topic])
- Re-evaluate your problem definition (eg, Is your signal band really 0-3 kHz, or is it more like 2 kHz-3 kHz? You may be able to change your output filter to improve performance in the latter case)
Also, how many bits of precision do you really need? Knowing this will help decide which of the above options has the potential to help.
Hello,
Thank you for the response. Sorry, I forgot to mention sampling frequency.
ADC sampling frequency = 16Mhz.(Its not 1.563Mhz)
Filter sampling frequency = 30Mhz.
The maximum input signal range that can be represented is 0-20khz.
Okay, so redoing the math with that:
ENOB = IW + 0.5 * log(0.5 * FS / BW) / log(2) [bits]
ENOB = 8 + 0.5 * log(0.5 * 30 MHz / 20 kHz) / log(2) [bits]
ENOB = 8 + 4.78 [bits]
ENOB = 12.78 [bits]
The main question still stands, how many bits do you need? And probably a better way to phrase it: how much SNR do you need?
Hello,
As I said in other post, the sampling frequency of 8-bit ADC is 1.563Mhz. For this, the SINAD and ENOB of ADC output achieved was ~37dB and ~5 bits respectively. In order to achieve higher SINAD and ENOB values, I'm increasing the ADC sampling frequency to 16Mhz and filtering it with 30MHz. There's no expectation of specific SINAD and ENOB value. For a designed filter specs, I want to know if I'm getting correct ENOB.
Please help me the following doubts.
1. The accumulator/output bit width is IW+LGMEM=22. But the ENOB of filter output is 11.7. What could be the reason? Why I'm not able to achieve more than 11 bits?
2. For ADC sampling frequency of 16Mhz, I took filter frequency as 30Mhz. If I take more than 30Mhz, I dont see sine wave ie., filtered output. What's the reason? Is there any rule to select filter sampling frequency w.r.to ADC sampling frequency?
ADC samples at 16MHz yet filter cut-off is at 30MHz??? this is just not right
Hi,
@kaz
I took filter sampling frequency as 30Mhz. The maximum input signal frequency achieved is 35khz
Sorry but your words and description are not helpful. Your filter is meant to filter adc data so must be working at same sampling frequency. The filter frequency response e.g. cut off is going to be fractional relative to this sampling frequency. what could be confusing you is these two words "frequency" as sampling rate (e.g. Msps) and "frequency" as true frequency(e.g. MHz).
I'm also feeling a bit confused here. What do you mean by "filter sampling frequency," and how can it be higher than the input frequency of the ADC? I think there may be a misunderstanding here on what you are doing, and that probably means my earlier calculations were wrong.
Let's try to get on the same page here. Please correct the values I think you are working with.
ADC Sampling frequency: 16 MHz
ADC Bits: 8 bits/sample
ADC ENOB: ~5 bits/sample
Filter: Running block average
Averaged samples: 16384 (2^14)
As to the question of ENOB vs the necessary accumulator width, these are measuring two different quantities, despite both having units of [bits]. ENOB is fundamentally a measure of signal-to-noise ratio, so there needs to be a scale factor of 1/2 to account for the incoherent addition of noise. I think that may be what you are missing.
I’m sorry, Ill try to explain.
I’m taking ADC reading for every 0.6µs(Fs=16MHz). This output is given to filter. Filter is running at 30MHz clock. So, it samples the ADC output for every 0.33µs(1/(30MHz)).
@therationalpi
You wrote the formula to calculate ENOB. Could you please attach the reference? I couldn’t find it.
I've found formulas in a number of places stated in different ways, but pg 8 in this pdf has it stated pretty simply:
https://www.silabs.com/documents/public/application-notes/an118.pdf
As for your ADC and filter sampling, I feel like the mismatch of the ADC and polling rate could cause you some problems. Aren't you going to capture the same value from the ADC twice in a row sometimes and only once at others? That's going to add a lot of noise to your data!
Hi Adira, just for my understanding (to be able to follow the thread...):
ADC reading every 0.6µs -> 1 /1.6MHz means you're sampling with a sample rate Fs=1.6MSps, not 16 MHz. Is this a math error?
Even, if your ADC is sampling the values at 16 MSps, but you take only one every 0.6 µs, you work only with a sample rate of 1.6MSps.
In the same way you mention 0.33µs(1/(30MHz)). My brain calculator always outputs this: 0.33µs=1/(3MHz), ignoring the rounding issue.
Then, if you filter with a higher rate than sampling, you're using samples more than once, don't you. (but not every one...)
Is this wrong math, or did I just misunderstand what you're trying to tell?
Hello,
Tracking ADC consist of three components. Comparator, counter and DAC. External board consist of Comparator and DAC. Counter is implemented in FPGA. External board is interfaced with FPGA. Counter is running at 1.563MHZ clock. Counter reads the comparator value for every 1.563Mhz. So ADC sampling frequency or sampling rate is 1.563Mhz. Isn't the sampling rate and sampling frequency are same? Please correct me if I'm wrong.
I changed the filter frequency to 16Mhz.
So ... your 0.6 µs is really (1/1.563MHz) ??
OK. And you're doing proper upsampling to 16 MHz?
For example with zero stuffing between the real values ...
And you certainly have filtered your analog input signal for an appropriate bandwidth of < (1.563MHz)/2 .
In this case I would be satisfied with your setup...
I have few doubts.
1. I took Number of taps N= 2^14. I took that value after evaluating ADC with many values. How to decide number of taps for a particular sampling frequency?
2. For simple moving average filter, I took oversampling frequency of 6.25Mhz i.e., 4 times my sampling frequency(1.563Mhz) and N=8. 1 bit precision is gained. Does the prevision increase if I increase number of taps to large value?
Even though the ADC sampling frequency is 1.563Mhz, the maximum analog signal frequency that can be represented for 8 bit ADC is less than 5khz. It's not half the sampling frequency. Could you please explain what could be reason for it?
A simple ADC averaging process increases resolution by n bits for each 4^n sample averages. So 2^14 averages or 4^7 gives 7 more bits enob i.e turns 5 bits into 12 bits. Apart from losing 0.25 bit for the real world your 11.75 bits sounds about right.
Thank you for your response. I have a follow up question. Let's say that OW is just 8 bits instead of 14. Then according to your logic, 2^8 ie. 4^4 ..should turn ENOB of 5 bit into 5+4=9 ?
Also I have a basic question regarding ENOB. Can the ENOB exceed the number of ADC output bit width?
