How to avoid Blocking Statement in Verilog
Started by 4 years ago●1 reply●latest reply 4 years ago●74 viewsHi,
I have a matlab code and I have to convert it to verilog.The matlab code is as follows:
/****************************************************************/
clc;
clear all;
close all;
delt = 5;
carr_phase_s = 0;
for i = 1:1:30
carr_phase_s = carr_phase_s + delt;
if(carr_phase_s >= 26)
carr_phase_s = carr_phase_s - 26;
end
end
output in Matlab: 5 10 15 20 4 9 14 19 24 3 8 13 18 23 2 7 12 17 22 1 6 11 16 21 0 5 10 15 20
/*****************************************************************/
I have written a verilog equivalent for it. It is as follows:
module TestCode(
);
reg clk=0;
always#5 clk=~clk;
reg [2:0] delt=5;
reg [5:0] carr_phase_s=0;
always@(posedge clk)
begin
carr_phase_s<=carr_phase_s+delt;
carr_phase_s_d<=carr_phase_s;
if(carr_phase_s>=26)
begin
carr_phase_s_d<=carr_phase_s-26;
carr_phase_s<=carr_phase_s-26;
end
end
endmodule
Output in simulation of Xilinx ISE/Vivado software:
carr_phase_s_d =0 5 10 15 20 25 4 4 9 14 19 24 3 3 8 13 18 23 2 2 7 12 17 22 1 1 6 11 16 21 0 0 5 10 15 20
As, one can see there is repetition of the value whenever carr_phase_s is crossing the boundary.
Some one help me in properly converting this piece of code, so that the output of both Matlab and Verilog match perfectly?
Thanks.
I think this could be one way.
always@(posedge clk)
begin
if(carr_phase_s + delt >= 26)
carr_phase_s <= (carr_phase_s + delt) -26;
else
carr_phase_s<=carr_phase_s + delt;
end