Processing Gain at output of ADC

Started by rathnakarreddy 9 months ago2 replieslatest reply 9 months ago62 views

With adequate filtering after AD conversion, the SNR is calculated as,


N-> No: of ADC bits

The term 10log(fs/2*BW) is referred to as the Processing Gain. This processing Gain is acheived after filtering. 

Consider, the following case where fs=60MSPS and BandWidth =30KHz, and N=12

Process Gain=10*log(60MSPS/(2*30KHz))


This 30dB corresponds to 5 bits(Since 1 bit for 6dB)

So, at the output  of the filter, do  I need to maintain 5  extra bits .?

 That is to say, after AD conversion, input to filter will be 12 bits(Since ADC is 12 bits). So, output of the Filter does it need to be 17 bits(12+5)?

Any one please reply?


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Reply by kazJune 5, 2020

I answered you previously but you didn't seem to grasp my view.

The SNR equation you refer to is that of quantisation noise (SNRQ) and as measured using full scale single tone. 

It implies that SNRQ is function of "ONLY" bitwidth at ADC. It is the result of the fact that an error of 1/2 lsb is unavoidable when digitising an analogue signal.

If you stay at 12 bits anywhere (e.g. after filtering) you get snr of 12 bits only i.e. 72dB. You cannot filter off quantisation noise.

To get processing gain advantage you need to increase bitwidth by 5 bits to 17 through filtering/decimation.

I strongly believe you cannot get 72+30 dB from keeping at 12 bits no matter what you do.

Note: compare filtering/decimation to directly changing 12 bits to 17 bits by just scaling by 2^5. You will be inserting 5 nice useless zeros in lsbs and snr stays as 72 dB since data and error get scaled equally. The filtering method helps insert useful values instead of zeros in those lsbs, these new values are acquired from adjacent samples before decimation.

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Reply by asserJune 5, 2020

Really, gain is 5 bits. But in conditions when the signal has not the DC component. If you needn't such a gain you can truncate the resulting bit width to the desired value. Note, that the inner filter structure must contain the increased bit width taking into account the computation error accumulation, overflow prevention.