Hello, 

I have designed a FIR Fractional Rate Converter Filter by using FIR Compiler. The purpose of the design convert 20MHz(20M samples) to 20.48MHz(20.48M samples) and to reach valid data continuity in the output. However, there is problem with the input. The IP expects valid data in each 1 clock cycle and gives valid output data in every clock cycle. I use an Asynchronous Fifo to change 20MHz to 20.48MHz in the output. In some cases the Fifo can't supply valid data to the input as expected and s_axis_tready is always high. So, this situtation breaks valid data continuity at the output port. How can I solve this problem ? 

Filter Options and Channel Spesifications 

Filter Type --> Interpolation 

Rate Change Type --> Fixed Fractional 

Interpolation Rate Value --> 128 

Decimation Rate Value --> 125 

Input Sampling Frequency --> 20MHz

Clock Frequency --> 20.48MHz

Clock Cycles Per Input --> 1  !!(How can I supply with 20 MHz ? The main clock is 20.48Mhz, and s_axis_tready is always high.)

Clock Cycles Per Output --> 1

Thank you. 

Try let the filter control its input read from fifo. I assume it has that sort of ready signal.