Efficient implementation of FIR filters on a FPGA
Started by 5 years ago●2 replies●latest reply 5 years ago●173 viewsThis thread discusses an efficient method for implementing Finite Impulse Response (FIR) filters on Xilinx FPGAs by leveraging dedicated DSP slices. The approach aims to maximize performance by treating these slices as high-speed processing blocks within the FPGA fabric.
The discussion highlights that utilizing DSP-specific resources leads to faster designs, drawing comparisons to historical implementation tools like DSPBuilder.
- Implementing FIR filters specifically within DSP slices optimizes processing speed and resource usage.
- The technique creates a high-efficiency 'ASIC island' effect within the FPGA fabric.
- Using dedicated DSP blocks for both single and multirate filters consistently results in faster designs compared to logic-based implementations.
Hello there,
I made a short video in which I present a way to implement FIR filters on FPGA (Xilinx) by using only DSP slices. You can check it out here:
PS:
I'd be glad if you give me some feedback.
Also, is this the correct way to post content should I decide to do this more often?
Thanks for the video.
It is good corner you pointed at. In the 2010s I used DSPBuilder for various FIR filters (single or multirate) and noticed that in many occasions it was implementing the filtering computations on dsp blocks only. The result was very fast designs.
It sounds like doing a design in a small Asic island within fpga.
Kaz
Noted :)
