Implementing a folded FIR on FPGA

Started by DHMarinov 9 months ago2 replieslatest reply 9 months ago69 views

Hello there,

This is a follow up video about FIR filter design on FPGA. It goes into the implementation of a folded FIR as well as some aspects the design.
You can check it out here:


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Reply by kazFebruary 5, 2021


Just pointing out that your video about manual dsp based design is intuitive for study and beginners. some minor issues with pre-adder: it increases data width by one bit at multiplier input (not a problem here). polyphase subfilters for upsampling will also lose symmetry and so preadder will not apply.

In actual industry we use ip core for filter and forget about manual design as it is quicker. after all we do a lot of ip based work that come at no extra license cost.

I will not say same for sysgen as it is a bit complicated platform but ip cores can do whatever structure is best for fpga target.

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Reply by DHMarinovFebruary 7, 2021

Hi kaz,

I'll take a look at the polyphase filters and the more high-level approaches later on.