RC-filter in VHDL

Started by Aida92 1 year ago1 replylatest reply 1 year ago97 views

Hello everyone!

I am trying to implement Raised-cosine filter in VHDL. In the current simulation I am using the standard method of the filter simulation:

- create an array with filter coefficients

- add and mult

I would like to optimise the simulation.

Does anyone has an example how I can implement the filter? Is there another way to implement it?

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Reply by kazApril 16, 2021

Hard to get details of your add-mult

There are ways to reduce any filter:

Either using LUT if input levels are few and fixed e.g. QAM. so mult results can be precomputed and inserted in a table to be addressed by input.

Or if upsampling/downsampling and filtering at same time then you can reduce resource a lot but requires good grasp of these concepts.

Or have a clock speed multiple of sample rate to share same resource across available clock ratio.