Sha256 on FPGA board

Started by Iani97 1 year ago102 views

Hello guys,

I have been trying to implement to implement the SHA256 algorithm on my ARTY A7 35t using Vivado

I am using TeraTerm to send information to the board using the UART module..

As you can see my paths arent failing (they is some logic level between them and some Fanout, but they arent failing so i assume it is ok).My simulation look alright. THe only problem i can see is that i didnt constrain the input and output delay, but i dont understand how they work exactly or even if they are needed. When i program the board with the Uart module on its own, everyhitng work alright, so i am quite stuck. If you could give me some advice i wiould be very thankful. I will attach my Verilog code and screenshots of the Timing analysis in Synthesis and after Implementation.

Thank you in advance.

sendBytes.v.txttiming implementation analysis_97195.png

timing sumarry synthesis_99374.png