A user is seeking a method to manage Zynq-7000 processing system components within a Vivado non-project mode workflow without utilizing the GUI. The discussion focuses on how to automate the generation of block design sources for integration into custom Makefiles.
The recommended solution is to use the 'Export Block Design' feature to generate a Tcl script, which can then be manually edited to remove project-specific commands while retaining IP configuration logic.
- Vivado's 'Export Block Design' command generates a Tcl script that recreates the processing system configuration.
- The generated Tcl script contains both project-specific setup and the logic required to instantiate IP cores.
- Users can manually strip project-related commands from the exported script to integrate it into a pure non-project flow.
- Non-project mode requires manually managing the synthesis and implementation of the generated block design files.
I'd like to use Vivado in non-project mode, using makefiles and Tcl scripts. However, my chip is a Zynq-7000 SoC where Vivado needs to generate a module representing the processing system component with all of its AXI ports and other signals that go to the FPGA proper.
I know how to do that in project mode, but can't figure it out for the non-project mode.
Does anyone have any experience of that?
Any help would be much appreciated.
Thanks!
Hallo Kocsonya,
Vivado offers a way to this. Just follow te steps (see image below):
- Open the desired block design
- go to the menu: file -> export
- select "Export Block Design"
- vivado will open a new window and ask you to enter a name directory for the tcl file
Cheers,
Rafael.
Rafael,
Thanks for answering, but the point of the exercise is not to open the GUI. I know that method. The Tcl file it writes out is a project mode representation of the block design. That is, when you pass that Tcl file to Vivado, it will then create a directory with lots of files in it.
What I'd like to know if I can do that without opening the GUI. Have a Tcl file which creates just a single Verilog file which contains a module representing Zynq's internal ports to the FPGA and nothing else. No GUI, no project creation, no Vivado maintaining sources.
Thanks again,
Kocsonya
