I am designing an Ethernet pass-through system using two FPGAs and external PHYs.

Each FPGA has two Ethernet PHY interfaces, as we know single FPGA pass-through (PHY1 ↔ FPGA ↔ PHY2) works correctly.

Now I want to implement a cross-connected topology using two FPGAs as follows:

Device A ↔ PHY1 ↔ FPGA1 ↔ PHY2 ↔ Device B and Similarly Device B ↔ PHY2 ↔ FPGA2 ↔ PHY1 ↔ Device A. Is this architecture feasible in practice for Ethernet communication? if Yes, How can implement this. Thank You Praveen

Hello,

If I understand the behaviour correctly, I would say it depends on the interface you use into your FPGA (MII/GMII, PCS, LVDS, GXB).

That said, I think you’ll need at least some logic to make things work: either by using a multiplexer on your board or via an FPGA (in which case, the code will likely be different, unless you’ve designated an address as an input pin)

Hope this helps.

Thanks for your reply....!! I am using GMII/RGMII interface into FPGA and my requirement here is Connecting PHY1 TX to FPGA1 RX and FPGA1 TX to PHY2 RX Directly Similarly PHY2 TX to FPGA2 RX and FPGA2 TX to PHY1 RX Directly. Is there any changes with MAC because as each FPGA connected to two PHY IC. Any idea or solution to this problem.

Sorry for the delay...

A picture is worth a thousand words (see above).

If this picture is OK, I do not see any problem (even if I do not clearly understand the purpose). This can be confusing because answers to some commands (such as ICMP) will be received by other FPGA...

MAC addresses are configured with MDIO interface, so one FPGA can configured both PHY (or each FPGA can configure its own PHY). For FPGA transmission, it should be generated with the correct MAC/IP address (so pay attention to ICMP answer for example)...