Generating a Block Design in Vivado from existing Verilog & IP files
Started by 10 years ago●2 replies●latest reply 10 years ago●7309 viewsA user is seeking a way to generate a Vivado Block Design from legacy Verilog and IP files to enable hardware handoff to SDK. The discussion explores whether a visual Block Design is strictly necessary for generating the required .hwdef and .sysdef files for software development.
The consensus suggests either packaging existing Verilog as custom IP using Vivado's IP Packager or bypass the Block Design entirely by using a HDL top-level wrapper for instantiation.
- Vivado requires specific hardware handoff files for SDK which are typically generated via a Block Design.
- Legacy Verilog files can be converted into reusable blocks using the IP Packager (referencing UG1119 and UG1118).
- A HDL top-level file can be used to manually instantiate and connect all modules as an alternative to the Block Diagram editor.
- Successful synthesis and implementation do not automatically guarantee the creation of hardware handoff files without a defined design hierarchy.
I have a #Vivado project that I pieced together from #Verilog and IP files from a Github repository. I believe the project was originally created in ISE as there is no Tcl file to run and regenerate the original block design from. I am looking for a way to generate the block design from the existing Verilog and IP because even though I am able to synthesize the project, run implementation, and generate a bitstream, I am unable to export the bitstream to SDK because without a block design, the .sysdef and .hwdef files are never created so there is no hardware handoff for the SDK. I even tried running the Tcl commands to force Vivado to generate the .sysdef and .hwdef files despite the fact the commands are automatically run after generation of the bitstream and implementation, and I am still unable to export the bitstream to SDK.
I have been through many forums and I'm beginning to think I may be trying to do the impossible here. I was curious if anyone else had found a work-around.
Hi,
I think you should first package your own Verilog IPs into IPXact and then recreate the block design.
In order to do so you have the User Guide UG1119 and the associated tutorial UG1118.
Regards
Olivier
wlarsen
If you have all HDL files in verilog or VHDL you can just write a top level file which performs the instantiation and port mapping (to use VHDL terms) and connects the modules together you do not have to use the Block Diagram editor to create your design.
It should then synthesise and implement OK - after all the block diagram results in a HDL file being created for implementation anyway.
Hope this helps
Adam
